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    Memory circuit and method of operating same
    12.
    发明授权
    Memory circuit and method of operating same 有权

    公开(公告)号：US11238908B2

    公开(公告)日：2022-02-01

    申请号：US17076965

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Cheng Hung Lee ,  Shih-Lien Linus Lu

    IPC: G11C11/4076 ,  G11C11/4094 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/419

    Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.

    SRAM power-up random number generator
    13.
    发明授权
    SRAM power-up random number generator 有权

    公开(公告)号：US11049555B1

    公开(公告)日：2021-06-29

    申请号：US16869856

    申请日：2020-05-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Chen-Lin Yang ,  Yu-Hao Hsu ,  Shih-Lien Linus Lu

    IPC: G11C11/418 ,  G11C7/12 ,  G06F7/58 ,  G11C5/14 ,  G11C8/08

    Abstract: A memory device includes a plurality of bit lines, a plurality of word lines, and a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines. Each of the bit cells is configured to present an initial logic state on the bit lines. A power supply terminal is coupled to the memory cell array. A controller is coupled to the word lines and the bit lines, and is configured to, during a RNG phase, precharge the bit lines to a second voltage level lower than a first voltage level, and determine the initial logic states of the plurality of bit cells to generate a random number. The first voltage level is a voltage level for operating the memory cell array during an SRAM phase.

    Memory macro disableable input-output circuits and methods of operating the same
    14.
    发明授权
    Memory macro disableable input-output circuits and methods of operating the same 有权

    公开(公告)号：US10186313B2

    公开(公告)日：2019-01-22

    申请号：US15140726

    申请日：2016-04-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Pankaj Aggarwal ,  Jui-Che Tsai ,  Ching-Wei Wu

    IPC: G11C11/419 ,  G11C7/18 ,  G11C11/418 ,  G11C7/10

    Abstract: A memory macro includes a first input terminal, a first memory cell array, a second memory cell array, a first input output (IO) circuit, a second IO circuit, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first set of driver circuits are coupled to the first memory cell array and the first IO circuit. The second set of driver circuits are coupled to the second memory cell array and the second IO circuit. The logic circuit has a first terminal coupled to the first input terminal and configured to receive a first signal. The logic circuit is coupled to the first set of driver circuits and the second set of driver circuits. The logic circuit is configured to generate at least a second signal responsive to the first signal causing a change in the operational mode of the memory macro.

    Memory circuit and method for routing the memory circuit
    15.
    发明授权
    Memory circuit and method for routing the memory circuit 有权
    记忆电路和路由存储器电路的方法

    公开(公告)号：US09490005B2

    公开(公告)日：2016-11-08

    申请号：US13790829

    申请日：2013-03-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Cheng Hung Lee ,  Jui-Che Tsai ,  Ching-Wei Wu ,  Kuang Ting Chen

    IPC: G11C11/41 ,  G11C5/06 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11

    CPC classification number: G11C11/41 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

    Abstract: A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line.

    Abstract translation: 存储器电路包括第一行存储器单元，第一字线和第二字线，并且电耦合到第一行存储器单元，第二行存储器单元沿着预定方向与第一行存储器单元对准 ，以及第三字线和第四字线，并且电耦合到第二行存储器单元。 第一字线与第三字线对齐，第二字线与第四字线对齐。 第一字线或第二字线之一与第三字线或第四字线之一电耦合。 第一字线或第二字线中的另一个与第三字线或第四字线中的另一个电分离。

    Balanced negative bitline voltage for a write assist circuit
    16.
    发明授权
    Balanced negative bitline voltage for a write assist circuit 有权

    公开(公告)号：US12087345B2

    公开(公告)日：2024-09-10

    申请号：US17542938

    申请日：2021-12-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Chia-Cheng Chen ,  Yih Wang

    IPC: G11C11/24 ,  G11C7/12 ,  G11C11/419

    CPC classification number: G11C11/24 ,  G11C7/12 ,  G11C11/419

    Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

    MEMORY DEVICE
    19.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210350847A1

    公开(公告)日：2021-11-11

    申请号：US16870030

    申请日：2020-05-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hidehiro Fujiwara ,  Chia-En Huang ,  Yen-Huei Chen ,  Jui-Che Tsai ,  Yih Wang

    IPC: G11C11/419 ,  G11C7/12

    Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

    SRAM POWER-UP RANDOM NUMBER GENERATOR
    20.
    发明申请
    SRAM POWER-UP RANDOM NUMBER GENERATOR 有权

    公开(公告)号：US20210350845A1

    公开(公告)日：2021-11-11

    申请号：US17359994

    申请日：2021-06-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Chen-Lin Yang ,  Yu-Hao Hsu ,  Shih-Lien Linus Lu

    IPC: G11C11/418 ,  G11C7/12 ,  G06F7/58 ,  G11C5/14 ,  G11C8/08

    Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

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