-
公开(公告)号：US12169679B2
公开(公告)日：2024-12-17
申请号：US18362195
申请日：2023-07-31
Inventor： Shao-Lun Chien , Pin-Dai Sue , Li-Chun Tien , Ting-Wei Chiang , Ting Yu Chen
IPC: G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394
Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.
-
公开(公告)号：US11983475B2
公开(公告)日：2024-05-14
申请号：US18165411
申请日：2023-02-07
Inventor： Pin-Dai Sue , Po-Hsiang Huang , Fong-Yuan Chang , Chi-Yu Lu , Sheng-Hsiung Chen , Chin-Chou Liu , Lee-Chung Lu , Yen-Hung Lin , Li-Chun Tien , Yi-Kan Cheng
IPC: G06F30/00 , G06F30/373 , G06F30/392 , G06F30/394 , G06F111/20
CPC classification number: G06F30/392 , G06F30/373 , G06F30/394 , G06F2111/20
Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
-
公开(公告)号：US11790151B2
公开(公告)日：2023-10-17
申请号：US17885106
申请日：2022-08-10
Inventor： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC classification number: G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
-
公开(公告)号：US11216608B2
公开(公告)日：2022-01-04
申请号：US16664242
申请日：2019-10-25
Inventor： Chi-Yu Lu , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue , Yi-Hsin Ko
IPC: G06F30/392 , G06F30/398
Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.
-
公开(公告)号：US10950594B2
公开(公告)日：2021-03-16
申请号：US16420919
申请日：2019-05-23
Inventor： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC: H01L27/02 , G06F30/392 , H01L27/092 , H01L29/423 , H01L27/118
Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
-
Patent Agency Ranking
公开(公告)号：US12216981B2
公开(公告)日：2025-02-04
申请号：US18448143
申请日：2023-08-10
Inventor： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
-
公开(公告)号：US11862637B2
公开(公告)日：2024-01-02
申请号：US16879166
申请日：2020-05-20
Inventor： Shao-Lun Chien , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue
IPC: H01L27/092 , H01L27/088 , H01L21/8234 , H01L23/528 , H01L23/522 , H01L21/765 , H01L21/8238
CPC classification number: H01L27/0924 , H01L21/765 , H01L21/823412 , H01L21/823821 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L23/5286 , H01L27/088 , H01L27/092 , H01L27/0922
Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
-
公开(公告)号：US11768989B2
公开(公告)日：2023-09-26
申请号：US17558157
申请日：2021-12-21
Inventor： Chi-Yu Lu , Hui-Zhong Zhuang , Pin-Dai Sue , Yi-Hsin Ko , Li-Chun Tien
IPC: G06F30/392 , G06F30/398
CPC classification number: G06F30/392 , G06F30/398
Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.
-
公开(公告)号：US11727187B2
公开(公告)日：2023-08-15
申请号：US17689825
申请日：2022-03-08
Inventor： Shao-Lun Chien , Pin-Dai Sue , Li-Chun Tien , Ting-Wei Chiang , Ting Yu Chen
IPC: G06F30/398 , G06F30/392 , G06F30/394 , G03F1/36
CPC classification number: G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394
Abstract: A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.
-
公开(公告)号：US20190279975A1
公开(公告)日：2019-09-12
申请号：US16420919
申请日：2019-05-23
Inventor： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC: H01L27/02 , H01L27/092 , H01L29/423 , G06F17/50
Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.02 seconds)
