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公开(公告)号：US20230109928A1
公开(公告)日：2023-04-13
申请号：US18077536
申请日：2022-12-08
Inventor： Tsann Lin , Ji-Feng Ying , Chih-Chung Lai
Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
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公开(公告)号：US11532339B2
公开(公告)日：2022-12-20
申请号：US16902218
申请日：2020-06-15
Inventor： Jui-Fen Chien , Hanwen Yeh , Tsann Lin
Abstract: A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.
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公开(公告)号：US20220216269A1
公开(公告)日：2022-07-07
申请号：US17703923
申请日：2022-03-24
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
IPC: H01L27/22 , H01L23/528 , H01L43/12 , H01L43/02 , H01F10/32 , H01L23/522 , H01F41/32 , G11C11/16
Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
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14.发明申请公开(公告)号：US20210359002A1
公开(公告)日：2021-11-18
申请号：US17388394
申请日：2021-07-29
Inventor： Tsann Lin , Chien-Min Lee , Ji-Feng Ying
Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode layer over a substrate. A first etch process is performed, thereby defining one or more holes in the bottom electrode layer and defining a bottom electrode. A pair of insulators are formed within the one or more holes such that the insulators are disposed on opposing sides of the bottom electrode. A buffer layer, a seed layer, a magnetic tunnel junction (MTJ) stack, and a top electrode are formed over the bottom electrode. A second etch process is performed to remove a portion of the buffer layer, the seed layer, the MTJ stack, and the top electrode, thereby defining a memory cell.
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公开(公告)号：US11716909B2
公开(公告)日：2023-08-01
申请号：US17070426
申请日：2020-10-14
Inventor： Ya-Ling Lee , Tsann Lin , Han-Jong Chia
CPC classification number: H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MU element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TIM coefficient desired for a low bit-error-rate (BER) read operation.
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Patent Agency Ranking
公开(公告)号：US12069961B2
公开(公告)日：2024-08-20
申请号：US18331154
申请日：2023-06-07
Inventor： Ya-Ling Lee , Tsann Lin , Han-Jong Chia
CPC classification number: H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240062794A1
公开(公告)日：2024-02-22
申请号：US18499423
申请日：2023-11-01
Inventor： Tsann Lin , Ji-Feng Ying , Chih-Chung Lai
CPC classification number: G11C11/161 , H01F10/3259 , H01F10/3286 , H01F41/34 , H10B61/22 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
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公开(公告)号：US11825664B2
公开(公告)日：2023-11-21
申请号：US17703923
申请日：2022-03-24
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
IPC: H10B61/00 , H10N50/80 , H01L23/528 , H01F10/32 , H01L23/522 , H01F41/32 , G11C11/16 , H10N50/01
CPC classification number: H10B61/22 , G11C11/161 , H01F10/329 , H01F10/3259 , H01F41/32 , H01L23/528 , H01L23/5226 , H10N50/01 , H10N50/80
Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
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公开(公告)号：US20230369438A1
公开(公告)日：2023-11-16
申请号：US17740376
申请日：2022-05-10
Inventor： Neil Quinn Murray , Kuo-Chang Chiang , Mauricio MANFRINI , Tsann Lin
CPC classification number: H01L29/4908 , H01L27/1207 , H01L29/66969 , H01L29/7869
Abstract: A transistor includes a gate electrode, a gate dielectric layer, a short range order layer, a channel layer, and source/drain regions. The gate dielectric layer is disposed over the gate electrode. The short range order layer is disposed between the gate electrode and the gate dielectric layer. The short ranger order layer has slanted sidewalls. The channel layer is disposed on the gate dielectric layer. The source/drain regions are disposed on the channel layer.
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公开(公告)号：US12035636B2
公开(公告)日：2024-07-09
申请号：US18140472
申请日：2023-04-27
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
CPC classification number: H10N50/80 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01F10/3254 , H01F10/329 , H10B61/22 , H10N50/01 , H10N50/85 , H10N52/80
Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
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