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公开(公告)号：US20180123607A1
公开(公告)日：2018-05-03
申请号：US15691827
申请日：2017-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das , Brian Roger Elies
Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.
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公开(公告)号：US09846185B2
公开(公告)日：2017-12-19
申请号：US14189447
申请日：2014-02-25
Applicant: Texas Instruments Incorporated
Inventor： Krishnasawamy Nagaraj , Paul Kimelman , Abhijit Kumar Das
IPC: G01R27/26
CPC classification number: G01R27/2605
Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.
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公开(公告)号：US09780798B1
公开(公告)日：2017-10-03
申请号：US15339931
申请日：2016-11-01
Applicant: Texas Instruments Incorporated
Inventor： Abhijit Kumar Das , Brian Roger Elies
Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.
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公开(公告)号：US20170146633A1
公开(公告)日：2017-05-25
申请号：US14951902
申请日：2015-11-25
Applicant: Texas Instruments Incorporated
Inventor： Abhijit Kumar Das , Christy Lee She
IPC: G01R35/00
CPC classification number: G01R35/005
Abstract: A calibrated measurement circuit, with a first node, a second node, a circuit element coupled between the first node and the second node, and a reference circuit element. The calibrated measurement circuit also comprises circuitry for directing a first current and a second current between the first node and the second node and to the reference circuit element. The calibrated measurement circuit also comprises circuitry for measuring voltage across the circuit element in response to the first and second currents, and circuitry for measuring voltage across the reference circuit element in response to the first and second currents. A calibration factor is also determined for calibrating measured voltages across the circuit element, in response to a relationship between the first voltage, the second voltage, and the reference circuit element.
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公开(公告)号：US09520881B1
公开(公告)日：2016-12-13
申请号：US14927803
申请日：2015-10-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das , Krishnasawamy Nagaraj , Rahul Bhandarkar
IPC: H03L7/02 , H03K3/0231 , H03K3/011
CPC classification number: H03L7/02 , H03K3/011 , H03K3/0231 , H03L7/089
Abstract: A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration logic. The calibration logic is configured to receive an output of the comparator and control an on time and an off time of an oscillator based on the output of the comparator.
Abstract translation: 用于调谐振荡器频率的系统。 该系统包括修整的校准电路，其包括比较器和修整的延迟元件和校准逻辑。 校准逻辑被配置为接收比较器的输出，并且基于比较器的输出来控制振荡器的接通时间和关断时间。
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Patent Agency Ranking
公开(公告)号：US11996850B2
公开(公告)日：2024-05-28
申请号：US17673224
申请日：2022-02-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das
IPC: H03K5/24
CPC classification number: H03K5/249
Abstract: A device includes a first transistor (M1) having a control terminal that is a first comparator input, a first terminal that can be coupled to a voltage source, and a second terminal that provides a first comparator output; a second transistor (M2) having a control terminal that is a second comparator input, a first terminal that can be coupled to the voltage source, and a second terminal that provides a second comparator output; a third transistor (M3) having a control terminal coupled to M1, and a first terminal coupled to ground; a fourth transistor (M4) having a control terminal coupled to M2, and a first terminal coupled to ground; first switches that couple M3 second terminal to M3 control terminal, and M4 second terminal to M4 control terminal; and second switches that couple M3 second terminal to the M2 second terminal, and M4 second terminal to the M1 second terminal.
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公开(公告)号：US11658658B2
公开(公告)日：2023-05-23
申请号：US17700230
申请日：2022-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das , Brian Roger Elies
IPC: H03K17/687
CPC classification number: H03K17/6871
Abstract: In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.
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公开(公告)号：US11646750B2
公开(公告)日：2023-05-09
申请号：US17490138
申请日：2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das
CPC classification number: H03M1/462 , H03M1/1245 , H03M1/362 , H03M1/466
Abstract: An analog-to-digital converter (ADC) is provided. In some examples, the ADC includes a first reference voltage supply input, a second reference voltage supply input, a comparator comprising an input node, and a first reference switch coupled between the second reference voltage supply input and the input node of the comparator. The ADC also includes a set of capacitors, where each capacitor of the set of capacitors comprises a first terminal. In addition, the ADC includes a second reference switch coupled between the first reference voltage supply input and the first terminal of each capacitor of the set of capacitors. The ADC further includes a third switch coupled between the input node of the comparator and the first terminal of each capacitor of the set of capacitors.
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公开(公告)号：US20220263500A1
公开(公告)日：2022-08-18
申请号：US17734227
申请日：2022-05-02
Applicant: Texas Instruments Incorporated
Inventor： Abhijit Kumar Das , Ryan Alexander Smith
IPC: H03K5/1252 , H03K17/16
Abstract: One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
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公开(公告)号：US10581438B2
公开(公告)日：2020-03-03
申请号：US15730787
申请日：2017-10-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das
Abstract: A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.
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