公开(公告)号：US12212331B2

公开(公告)日：2025-01-28

申请号：US17976369

申请日：2022-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christy Leigh She ,  Joonsung Park ,  Krishnasawamy Nagaraj ,  Srinivasa Chakravarthy

IPC: H03M1/06 ,  H03M1/08

Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

公开(公告)号：US20240146323A1

公开(公告)日：2024-05-02

申请号：US17976369

申请日：2022-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christy Leigh She ,  Joonsung Park ,  Krishnasawamy Nagaraj ,  Srinivasa Chakravarthy

IPC: H03M1/08

CPC classification number: H03M1/08

Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

公开(公告)号：US20190162590A1

公开(公告)日：2019-05-30

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20180335459A1

公开(公告)日：2018-11-22

申请号：US16048559

申请日：2018-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishnasawamy Nagaraj ,  Paul Kimelman ,  Abhijit Kumar Das

IPC: G01R27/26

CPC classification number: G01R27/2605

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

公开(公告)号：US12000876B2

公开(公告)日：2024-06-04

申请号：US16540546

申请日：2019-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishnasawamy Nagaraj ,  Paul Kimelman ,  Abhijit Kumar Das

IPC: G01R27/26

CPC classification number: G01R27/2605

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

公开(公告)号：US09846185B2

公开(公告)日：2017-12-19

申请号：US14189447

申请日：2014-02-25

Applicant: Texas Instruments Incorporated

Inventor： Krishnasawamy Nagaraj ,  Paul Kimelman ,  Abhijit Kumar Das

IPC: G01R27/26

CPC classification number: G01R27/2605

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

公开(公告)号：US09520881B1

公开(公告)日：2016-12-13

申请号：US14927803

申请日：2015-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijit Kumar Das ,  Krishnasawamy Nagaraj ,  Rahul Bhandarkar

IPC: H03L7/02 ,  H03K3/0231 ,  H03K3/011

CPC classification number: H03L7/02 ,  H03K3/011 ,  H03K3/0231 ,  H03L7/089

Abstract: A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration logic. The calibration logic is configured to receive an output of the comparator and control an on time and an off time of an oscillator based on the output of the comparator.

Abstract translation: 用于调谐振荡器频率的系统。 该系统包括修整的校准电路，其包括比较器和修整的延迟元件和校准逻辑。 校准逻辑被配置为接收比较器的输出，并且基于比较器的输出来控制振荡器的接通时间和关断时间。

公开(公告)号：US12072229B2

公开(公告)日：2024-08-27

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

CPC classification number: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20210389174A1

公开(公告)日：2021-12-16

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US11105676B2

公开(公告)日：2021-08-31

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.