公开(公告)号：US12057443B2

公开(公告)日：2024-08-06

申请号：US17687380

申请日：2022-03-04

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US09721849B2

公开(公告)日：2017-08-01

申请号：US15255341

申请日：2016-09-02

Applicant: Texas Instruments Incorporated

Inventor： Derek W. Robinson ,  Amitava Chatterjee

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L21/761 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66659 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/7833 ,  H01L29/7835

Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

公开(公告)号：US20160322263A1

公开(公告)日：2016-11-03

申请号：US15204428

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/10 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US20160079364A1

公开(公告)日：2016-03-17

申请号：US14944481

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L29/10 ,  H01L27/06

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

公开(公告)号：US20150294967A1

公开(公告)日：2015-10-15

申请号：US14750339

申请日：2015-06-25

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

Abstract translation: 公开了一种用于集成电路的半导体可控整流器（图4A）。 半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。 具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。 在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。 具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。 在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。 具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

公开(公告)号：US20150187760A1

公开(公告)日：2015-07-02

申请号：US14575552

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L27/07 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/167 ,  H01L21/265 ,  H01L29/732 ,  H01L29/08

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

Abstract translation: 一种集成电路和方法，其具有具有第一基极调谐扩散的深集电极垂直双极晶体管。 MOS晶体管具有第二基极调谐扩散。 第一基调谐扩散和第二基调谐扩散使用相同的植入物形成。

公开(公告)号：US09064726B2

公开(公告)日：2015-06-23

申请号：US13789477

申请日：2013-03-07

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/20 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US08975135B2

公开(公告)日：2015-03-10

申请号：US14301766

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Amitava Chatterjee ,  Imran Mahmood Khan

IPC: H01L21/8242 ,  H01L29/66 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L29/66181 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11558 ,  H01L28/60

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹 在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

公开(公告)号：US08933510B2

公开(公告)日：2015-01-13

申请号：US14142006

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Amitava Chatterjee ,  Imran Khan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823456

Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

Abstract translation: 可以通过将MOS晶体管和DEMOS晶体管的源/漏区相同的导电类型的掺杂剂通过MOS晶体管的栅极并通过栅极形成包含具有相同极性的MOS晶体管和DEMOS晶体管的集成电路 的DEMOS晶体管。 注入的掺杂剂从DEMOS晶体管栅极的漏极侧边缘封闭。 注入的掺杂剂在DEMOS晶体管栅极的DEMOS晶体管的扩展漏极的漂移区域内形成漏极增强区域。

公开(公告)号：US20140103440A1

公开(公告)日：2014-04-17

申请号：US13651783

申请日：2012-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amitava Chatterjee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28123 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/823828 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66568

Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

Abstract translation: 具有降低的亚阈值导通的金属氧化物半导体（MOS）晶体管及其制造方法。 在这些晶体管中制造晶体管栅极结构，其形状和尺寸与从隔离电介质结构和晶体管有源区之间的界面重叠到有源区上。 因此，在隔离到有源接口处不能获得最小通道长度导通，而是沿着该界面的通道长度基本上延长，从而减少断态传导。