ADAPTIVE BODY BIAS FOR VOLTAGE REGULATOR
    11.
    发明申请

    公开(公告)号:US20190146536A1

    公开(公告)日:2019-05-16

    申请号:US16247198

    申请日:2019-01-14

    Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.

    Methods and apparatus for full gate drive of multilevel DC-DC converter with full duty cycle operation

    公开(公告)号:US10014775B1

    公开(公告)日:2018-07-03

    申请号:US15390911

    申请日:2016-12-27

    Abstract: Methods and apparatus for bootstrap capacitor sharing in multilevel DC-DC converters are disclosed. In one example, a bootstrap capacitor voltage of the bootstrap capacitor can be alternately shared between respective control gates of a first high side primary switch and a central high side primary switch of the multilevel DC-DC converter at different times during a duty cycle of the multilevel DC-DC converter. In another example, the bootstrap capacitor voltage can be transferred to drive respective control gates of the first and central high side primary switches and can ensure full gate drive of the first and central high side primary switches to avoid channel resistance degradation thereof, even when the multilevel DC-DC converter is operated in a substantially full duty cycle mode.

    Transient-insensitive level shifter

    公开(公告)号:US10103261B1

    公开(公告)日:2018-10-16

    申请号:US15857214

    申请日:2017-12-28

    Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal, the second positive supply voltage being floating with respect to the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

    METHODS AND APPARATUS FOR FULL GATE DRIVE OF MULTILEVEL DC-DC CONVERTER WITH FULL DUTY CYCLE OPERATION

    公开(公告)号:US20180183330A1

    公开(公告)日:2018-06-28

    申请号:US15390911

    申请日:2016-12-27

    CPC classification number: H02M3/158 H02M1/08

    Abstract: Methods and apparatus for bootstrap capacitor sharing in multilevel DC-DC converters are disclosed. In one example, a bootstrap capacitor voltage of the bootstrap capacitor can be alternately shared between respective control gates of a first high side primary switch and a central high side primary switch of the multilevel DC-DC converter at different times during a duty cycle of the multilevel DC-DC converter. In another example, the bootstrap capacitor voltage can be transferred to drive respective control gates of the first and central high side primary switches and can ensure full gate drive of the first and central high side primary switches to avoid channel resistance degradation thereof, even when the multilevel DC-DC converter is operated in a substantially full duty cycle mode.

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