Overcurrent detector
    3.
    发明授权

    公开(公告)号:US09739811B2

    公开(公告)日:2017-08-22

    申请号:US14699554

    申请日:2015-04-29

    发明人: Gangqiang Zhang

    摘要: An overcurrent detector that includes a sense transistor connected to a sense resistor, a second transistor matched to the sense transistor and connected in parallel to a second resistor, and a voltage comparator coupled to the sense transistor and second resistor. The sense transistor is configured to connect in a same gate and source connection with a driver output transistor. The second transistor and second resistor are configured to receive a current reference and generate a voltage reference. The voltage comparator is configured to compare the voltage reference with a voltage drop across the sense resistor.

    REDUCING TRANSISTOR BREAKDOWN IN A POWER FET CURRENT SENSE STACK

    公开(公告)号:US20230006060A1

    公开(公告)日:2023-01-05

    申请号:US17682370

    申请日:2022-02-28

    IPC分类号: H01L29/78 H01L29/66

    摘要: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

    Sense circuit for voltage converter

    公开(公告)号:US09748842B1

    公开(公告)日:2017-08-29

    申请号:US15213217

    申请日:2016-07-18

    摘要: A system including a first power transistor including a gate, a second power transistor including a gate and connected in series with the first power transistor, wherein the connection between the transistors defines a switch node is disclosed. The system further includes a pulse width modulator (PWM) controller configured to assert control signals to the gates of the first and second power transistors, a high side sensing circuit coupled to the gate and a drain of the first power transistor. The system further includes a low side sensing circuit coupled to the gate and a drain of the second power transistor, and a track and hold circuit coupled to the high and low side sensing circuits and configured to couple sense signals from the high and low side sensing circuits.