公开(公告)号：US11789836B2

公开(公告)日：2023-10-17

申请号：US17462046

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

CPC classification number: G06F11/2733 ,  G06F9/4843 ,  G06F11/2242 ,  G06F13/1668 ,  G06F13/28

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US11276134B2

公开(公告)日：2022-03-15

申请号：US16847864

申请日：2020-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajat Sagar ,  Shashank Dabral ,  Anthony Lell ,  Brijesh Jadav

IPC: G06T5/40 ,  G06T1/20 ,  G06T1/60 ,  G06T5/00

Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

公开(公告)号：US20130243148A1

公开(公告)日：2013-09-19

申请号：US13888050

申请日：2013-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Anthony Lell ,  Raguram Damodaran

IPC: H03K21/00

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

Abstract translation: 提供了一个时钟分频器，其配置为将高速输入时钟信号除以奇数，偶数或分数分频比。 例如，输入时钟可以具有1GHz或更高的时钟周期频率。 输入时钟信号被分割以产生输出时钟信号，首先接收表示分频比N的除法因子值F，其中N可以是奇数或偶数整数。 分数指示符表示分数指示符为1时的分频比为N.5，当分数指示符为零时表示分频比为N。 对于分数除数，F被设置为2（N.5）/ 2，并且对于整数分频比，F被设置为N / 2。 当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。 当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。 当分数指示符表示分频比为N.5时，响应于计数指示符的每个断言，合成输出时钟信号的一个周期。 当分数指示符表示分频比是整数时，响应于计数指示符的两个断言，合成输出时钟信号的一个周期。