公开(公告)号：US11764740B2

公开(公告)日：2023-09-19

申请号：US17462930

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tyler James Archer ,  Joel Martin Halbert ,  Bharath Karthik Vasan

IPC: H03F3/04 ,  H03F3/26

CPC classification number: H03F3/04

Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.

公开(公告)号：US10931247B2

公开(公告)日：2021-02-23

申请号：US16357572

申请日：2019-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vadim Valerievich Ivanov ,  Bharath Karthik Vasan ,  Piyush Kaslikar ,  Srinivas K. Pulijala

IPC: H03F1/02 ,  H03F3/387 ,  H03F3/19

Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

公开(公告)号：US10511269B2

公开(公告)日：2019-12-17

申请号：US15995355

申请日：2018-06-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bharath Karthik Vasan ,  Srinivas K. Pulijala ,  Steven G. Brantley

IPC: H03F1/32 ,  H03F3/45 ,  H03F3/21

Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.

公开(公告)号：US10461706B1

公开(公告)日：2019-10-29

申请号：US15966946

申请日：2018-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven G. Brantley ,  Bharath Karthik Vasan ,  Srinivas K. Pulijala ,  Martijn Snoeij

IPC: H03F3/45 ,  H03F3/68 ,  H03F1/02 ,  H03F1/08

Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.

公开(公告)号：US09954496B2

公开(公告)日：2018-04-24

申请号：US15385200

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven G. Brantley ,  Bharath Karthik Vasan ,  John Lawrence Caldwell

IPC: H03F1/14 ,  H03F1/30 ,  H03F3/187 ,  H03G1/00 ,  H03G3/30 ,  H03F3/30 ,  H03F3/45

CPC classification number: H03F1/305 ,  H03F3/187 ,  H03F3/3069 ,  H03F3/45085 ,  H03F3/45596 ,  H03F2200/03 ,  H03F2200/375 ,  H03G1/0023 ,  H03G1/0088 ,  H03G3/3005 ,  H03G3/348

Abstract: At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.