公开(公告)号：US10861943B2

公开(公告)日：2020-12-08

申请号：US16216874

申请日：2018-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

公开(公告)号：US20200064394A1

公开(公告)日：2020-02-27

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

公开(公告)号：US10014231B1

公开(公告)日：2018-07-03

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L29/06 ,  H01L29/20 ,  G01R31/12 ,  H01L21/66 ,  H01L23/544 ,  H01L29/40 ,  H01L29/417 ,  H01L27/088 ,  G01R31/28

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20250040208A1

公开(公告)日：2025-01-30

申请号：US18910671

申请日：2024-10-09

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Nicholas S. Dellas

IPC: H01L29/15 ,  H01L21/02

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

公开(公告)号：US20240332369A1

公开(公告)日：2024-10-03

申请号：US18193391

申请日：2023-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Billy Alan Wofford ,  Ebenezer Eshun ,  Jungwoo Joh ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402

Abstract: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.

公开(公告)号：US20240204055A1

公开(公告)日：2024-06-20

申请号：US18067705

申请日：2022-12-17

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/1075 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/743 ,  H01L21/746 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A microelectronic device includes a lower buffer layer of III-N semiconductor material formed over a silicon substrate. A screen layer having free charge carriers is formed over the lower buffer layer. The microelectronic device may include an upper buffer layer of III-N semiconductor material formed over the screen layer. A gallium nitride field effect transistor (GaN FET) is formed over the screen layer. The GaN FET has a two-dimensional electron gas (2DEG) layer directly over at least a portion of the screen layer. The screen layer may include a doped layer of III-N semiconductor material, or a buried barrier layer with 2DEG layers in the lower and upper buffer layers. The screen layer is electrically connected to a current node, that is, a source node or a drain node, of the GaN FET.

公开(公告)号：US20230361222A1

公开(公告)日：2023-11-09

申请号：US17737515

申请日：2022-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sagnik Dey ,  Dhanoop Varghese ,  Dong Seup Lee

IPC: H01L29/8605 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/8605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66196 ,  H01L29/66166

Abstract: The present disclosure generally relates to a resistor structure having a charge control layer. In an example, an integrated circuit includes a semiconductor substrate, a dielectric layer, a first contact, a second contact, and a charge control layer. The semiconductor substrate includes a semiconductor hetero-structure. The dielectric layer is disposed over the semiconductor substrate. The first contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed through the dielectric layer and contacting the semiconductor hetero-structure. The second contact is disposed laterally separated from the first contact. The charge control layer is disposed over the semiconductor hetero-structure and laterally between the first contact and the second contact. At least a portion of the dielectric layer is disposed between the charge control layer and the semiconductor hetero-structure.

公开(公告)号：US20230343829A1

公开(公告)日：2023-10-26

申请号：US18347234

申请日：2023-07-05

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Nicholas S. Dellas

IPC: H01L29/15 ,  H01L21/02

CPC classification number: H01L29/151 ,  H01L21/02458 ,  H01L21/02532 ,  H01L21/02507

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

公开(公告)号：US11769824B2

公开(公告)日：2023-09-26

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/0891 ,  H01L29/42316

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20230094094A1

公开(公告)日：2023-03-30

申请号：US17491185

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Yoshikazu Kondo

IPC: H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes providing a GaN substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate, the heterojunction supporting a 2-dimensional electron gas (2DEG) channel in the GaN substrate. A composite surface passivation layer is formed over a top surface of the epitaxial layer, wherein the composite surface passivation layer comprises a first passivation layer portion formed proximate to a first region of the GaN device and a second passivation layer portion formed proximate to a second region of the GaN device. The first and second passivation layer portions are disposed laterally adjacent to each other over the epitaxial layer, wherein the first passivation layer portion is formed in a first process and the second passivation layer portion is formed in a second process.