公开(公告)号：US20220066975A1

公开(公告)日：2022-03-03

申请号：US17364672

申请日：2021-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Nagalinga Swamy Basayya AREMALLAPUR ,  Jaiganesh BALAKRISHNAN ,  Robert Clair KELLER

IPC: G06F13/42 ,  G06F13/16 ,  G06F1/12

Abstract: A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.

公开(公告)号：US20210391944A1

公开(公告)日：2021-12-16

申请号：US17462055

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay PENNAM ,  Vamsi Krishna KANDALLA ,  Brahmendra Reddy YATHAM ,  Shailesh WARDHEN ,  Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU

IPC: H04L1/00 ,  H04B1/04

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

公开(公告)号：US20210119622A1

公开(公告)日：2021-04-22

申请号：US17071302

申请日：2020-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Ram Narayan KRISHNA NAMA MONY ,  Pooja SUNDAR

IPC: H03K5/1252 ,  G06F1/10 ,  G11C19/28 ,  H03K19/21 ,  G06F1/08 ,  H03K5/00

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.

公开(公告)号：US20190178993A1

公开(公告)日：2019-06-13

申请号：US15834178

申请日：2017-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhash Chandra Venkata SADHU ,  Bharath PATIL ,  Jaiganesh BALAKRISHNAN

IPC: G01S7/486 ,  G01S17/89 ,  G01S17/10 ,  G01S7/484

Abstract: A three dimensional time of flight (TOF) camera includes a transmitter and a receiver. The transmitter is configured to generate an electrical transmit signal at a plurality of frequencies over an integration time period and generate a transmit optical waveform corresponding with the electrical transmit signal. The receiver is configured to receive a reflected optical waveform that is the transmit optical waveform reflected off of an object, integrate the reflected optical waveform over the integration time period, and determine a distance to the target object based on a TOF of the optical waveform. The integration time period includes exposure time periods. A length of each of the exposure time periods corresponds to one of the frequencies. The TOF is determined based on a correlation of the electrical transmit signal and the return optical waveform utilizing a correlation function with respect to the integration time period.

公开(公告)号：US20170324423A1

公开(公告)日：2017-11-09

申请号：US15392491

申请日：2016-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Jaiganesh BALAKRISHNAN

IPC: H03M7/30 ,  H03H17/06

CPC classification number: H03M7/6047 ,  H03D7/165 ,  H03D2200/0056 ,  H03H17/0664 ,  H03M7/3059

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

公开(公告)号：US20220231667A1

公开(公告)日：2022-07-21

申请号：US17463317

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh BALAKRISHNAN ,  Sriram MURALI ,  Kalyan GUDIPATI ,  Venkateshwara Reddy POTHAPU ,  Sarma Sundareswara GUNTURI

IPC: H03H11/04 ,  H04B1/40

Abstract: Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

公开(公告)号：US20220029657A1

公开(公告)日：2022-01-27

申请号：US17493943

申请日：2021-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Pooja SUNDAR ,  Harshavardhan ADEPU ,  Wenjing LU ,  Yeswanth GUNTUPALLI

IPC: H04B1/40 ,  H04B1/00

Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.

公开(公告)号：US20200327950A1

公开(公告)日：2020-10-15

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20200152284A1

公开(公告)日：2020-05-14

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind GANESAN ,  Jaiganesh BALAKRISHNAN ,  Nagarajan VISWANATHAN ,  Yeswanth GUNTUPALLI ,  Ajai PAULOSE ,  Mathews JOHN ,  Jagannathan VENKATARAMAN ,  Neeraj SHRIVASTAVA

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/14 ,  G11C17/16

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US20190273601A1

公开(公告)日：2019-09-05

申请号：US16417827

申请日：2019-05-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Srinivas Kumar Reddy NARU ,  Sarma Sundareswara GUNTURI ,  Nagalinga Swamy Basayya AREMALLAPUR

IPC: H04L7/00 ,  H03K5/14

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.