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    SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED DIE PAD AND SOLDER MASK DESIGN
    11.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED DIE PAD AND SOLDER MASK DESIGN 审中-公开

    公开(公告)号：US20200251436A1

    公开(公告)日：2020-08-06

    申请号：US16778250

    申请日：2020-01-31

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Guangxu Li

    IPC: H01L23/00 ,  H01L21/48

    Abstract: A described example includes a package substrate having an array of die pads arranged in rows and columns on a die mount surface, and having an opposing board side surface; a solder mask layer overlying the die mount surface; a first plurality of solder mask defined openings in the solder mask layer at die pad locations, the solder mask defined openings exposing portions of a surface of corresponding die pads, the surface facing away from the package substrate; and at least one non-solder mask defined opening in the solder mask layer at a die pad location, exposing the entire surface of the die pad and sidewalls of the die pad at the non-solder mask defined opening.

    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS
    14.
    发明申请
    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS 有权

    公开(公告)号：US20220254735A1

    公开(公告)日：2022-08-11

    申请号：US17679082

    申请日：2022-02-24

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Guangxu Li

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

    Package substrate with partially recessed capacitor
    15.
    发明授权
    Package substrate with partially recessed capacitor 有权

    公开(公告)号：US11289412B2

    公开(公告)日：2022-03-29

    申请号：US16795873

    申请日：2020-02-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

    IPC: H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48 ,  H01L23/48

    Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

    VIA INTEGRITY AND BOARD LEVEL RELIABILITY TESTING
    17.
    发明申请
    VIA INTEGRITY AND BOARD LEVEL RELIABILITY TESTING 审中-公开

    公开(公告)号：US20190393106A1

    公开(公告)日：2019-12-26

    申请号：US16015965

    申请日：2018-06-22

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Ethan Tilden Davis

    IPC: H01L21/66 ,  H01L21/48 ,  H01L23/498 ,  G01R31/28

    Abstract: Described examples provide a method to evaluate reliability of hail grid array products in which an interconnect stress test is performed that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board, and the reliability of ball grid array products manufactured using package substrate portions of the production panel is evaluated according to the results of the interconnect stress test. A test coupon includes a rigid core material layer, dielectric layers laminated between copper layers above and below the core material layer, conductive micro-vias that extend through at least one of the dielectric layers between two of the copper layers, and conductive land pads on an outer one of the dielectric layers, the conductive land pads individually contacting one of the micro-vias.

    INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE
    19.
    发明申请
    INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE 有权
    集成电路封装及其制造方法

    公开(公告)号：US20140138822A1

    公开(公告)日：2014-05-22

    申请号：US13682576

    申请日：2012-11-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jaimal Mallory Williamson ,  Nima Shahidi ,  Yaoyu Pang

    IPC: H01L23/498

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014

    Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.

    Abstract translation: 一种集成电路（IC）封装，包括具有具有IC管芯安装区域的顶表面和围绕安装区域的周边区域的衬底的器件，多个平行导体层，多个绝缘层和多个电镀通孔 延伸穿过导体层和绝缘层的孔（PTH）。 公开了其中某些PTH和/或导体层和/或绝缘层具有与其它层不同的CTE的各种衬底结构。 由于与基板和IC芯片之间的CTE失配相关联的基板翘曲和/或焊点损伤，各种结构可能减少电路故障。

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