公开(公告)号：US20240213209A1

公开(公告)日：2024-06-27

申请号：US18595443

申请日：2024-03-05

Applicant: Stroke Precision Advanced Engineering Co., Ltd.

Inventor： Yu-Min Huang ,  Sheng Che Huang ,  Chingju Lin ,  Wei-Hao Wang

IPC: H01L23/00 ,  B23K1/005 ,  B23K101/40

CPC classification number: H01L24/75 ,  B23K1/0053 ,  B23K1/0056 ,  H01L24/80 ,  H01L24/81 ,  B23K2101/40 ,  H01L2224/75263 ,  H01L2224/75283 ,  H01L2224/75705 ,  H01L2224/7598 ,  H01L2224/80224 ,  H01L2224/8023 ,  H01L2224/80815 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81224 ,  H01L2224/8123 ,  H01L2224/81815

Abstract: A method for transferring an electronic device includes steps as follows. A flexible carrier having a first surface on which the electronic device to be transferred is disposed and a second surface, a target substrate, a target substrate, and a light-transmissible pin having a pressing end are provided. The flexible carrier is spaced from the target substrate with the first surface thereof facing the target substrate. The flexible carrier is deformed by exerting the pin to press the second surface with the pressing end thereof at a position corresponding to the electronic device until the electronic device is in contact with the target substrate. An energy beam emitted from a light source standing outside the pin and then traveling through the pin and going out from the pressing end to bond the electronic device onto the target substrate is applied. The pin is released from pressing the flexible carrier.

公开(公告)号：US09867295B2

公开(公告)日：2018-01-09

申请号：US14148856

申请日：2014-01-07

Applicant: Dell Products L.P.

Inventor： Bhavesh Patel ,  Sandor Farkas ,  Wallace Huson Ables

IPC: H01L21/66 ,  H01L23/00 ,  G01R31/02 ,  G01R31/04 ,  H05K3/34 ,  G06F1/18 ,  B23K1/00 ,  B23K1/20 ,  B23K3/06 ,  B23K3/08 ,  H05K1/14

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K3/087 ,  G01R31/026 ,  G01R31/048 ,  G06F1/181 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16106 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17517 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/3512 ,  H05K1/144 ,  H05K1/145 ,  H05K2201/0221 ,  H05K2201/10022 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/159 ,  H05K2203/162 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Systems and methods for providing a ball grid array connection include providing a circuit board having a circuit board surface including a plurality of pads. A ball grid array component includes a plurality of solder balls. The ball grid array component is coupled to the circuit board to position each of the plurality of solder balls adjacent a respective one of the plurality of pads. A solder reflow process is then performed to produce a plurality of soldered connections from each of the plurality of solder balls and a respective one of the plurality of pads. At least one spacer member is provided between the ball grid array component and the circuit board during the solder reflow process to provide a mechanical stop between the ball grid array component and the circuit board and a minimum height for each of the plurality of soldered connections.

公开(公告)号：US20170316971A1

公开(公告)日：2017-11-02

申请号：US15653329

申请日：2017-07-18

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR. ,  Qin-Yi Tong

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

公开(公告)号：US09589941B1

公开(公告)日：2017-03-07

申请号：US14996715

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hua Chen ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/58 ,  H01L25/065

CPC classification number: H01L25/50 ,  G06K19/07745 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/58 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/49 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/81005 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: In an embodiment, a semiconductor structure includes a multi-chip package system (MCPS). The MCPS includes one or more dies, a molding compound extending along sidewalls of the one or more dies, and a redistribution layer (RDL) over the one or more dies and the molding compound. The semiconductor structure also includes at least one sensor coupled to the RDL, with the RDL interposed between the at least one sensor and the one or more dies. The semiconductor structure further includes a substrate having conductive features on a first side of the substrate. The conductive features are coupled to the RDL. The substrate has a cavity extending from the first side of the substrate to a second side of the substrate opposite the first side, and the at least one sensor is disposed in the cavity.

Abstract translation: 在一个实施例中，半导体结构包括多芯片封装系统（MCPS）。 MCPS包括一个或多个模具，沿着一个或多个模具的侧壁延伸的模塑料，以及在一个或多个模具和模塑料上的再分布层（RDL）。 半导体结构还包括耦合到RDL的至少一个传感器，其中RDL置于至少一个传感器和一个或多个管芯之间。 半导体结构还包括在衬底的第一侧上具有导电特征的衬底。 导电特征耦合到RDL。 衬底具有从衬底的第一侧延伸到与第一侧相对的衬底的第二侧的空腔，并且至少一个传感器设置在空腔中。

公开(公告)号：US09224712B2

公开(公告)日：2015-12-29

申请号：US14177348

申请日：2014-02-11

Applicant: International Business Machines Corporation

Inventor： Marcus E. Interrante ,  Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L21/30 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  B23K3/06

CPC classification number: H01L24/81 ,  B23K3/0623 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75983 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/2064 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/0665 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2221/68381 ,  H01L2224/83 ,  H01L2924/00

Abstract: An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.

Abstract translation: 包含第一组焊球的插入器结构放置在真空分配板附近，真空分配板具有平面接触表面和位于其中的多个开口。 然后通过真空分配板中的开口施加真空，使得第一组焊球悬挂在多个开口内，并且插入件结构符合真空分配板的平面接触表面。 包含第二组焊球的半导体芯片被固定到中介层结构的表面。 然后将衬底与包含第一组焊球的内插器结构的表面接触，然后可以进行焊料回流和底部填充处理。 使用上述真空分配板基本上消除了内插器结构的翘曲。

公开(公告)号：US20150340285A1

公开(公告)日：2015-11-26

申请号：US14813972

申请日：2015-07-30

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. ENQUIST ,  Gaius Gillman FOUNTAIN, JR. ,  Qin-Yi TONG

IPC: H01L21/768 ,  H01L27/06

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：US20150249062A1

公开(公告)日：2015-09-03

申请号：US14194057

申请日：2014-02-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ai-Tee Ang ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  B23K3/08 ,  B23K3/04 ,  B23K1/00 ,  B23K1/20

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K1/203 ,  B23K3/04 ,  B23K3/082 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/75101 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/755 ,  H01L2224/7565 ,  H01L2224/759 ,  H01L2224/7598 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/95 ,  H01L2924/01007 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/2026 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/75

Abstract: Reflow processes and apparatuses are disclosed. A process includes enclosing a package workpiece in an enclosed environment of a chamber of a reflow tool; causing an oxygen content of the enclosed environment of the chamber to be less than 40 ppm; and performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm. An apparatus includes a reflow chamber, a door to the reflow chamber, an energy source in the reflow chamber, and gas supply equipment coupled to the chamber. The door is operable to enclose an environment in the reflow chamber. The energy source is operable to increase a temperature in the environment in the reflow chamber. The gas supply equipment is operable to provide a gas to the reflow chamber.

Abstract translation: 公开了回流处理和装置。 一种方法包括将包装工件封闭在回流工具的室的封闭环境中; 导致室的封闭环境的氧含量小于40ppm; 并且在氧气含量小于40ppm时，在室的封闭环境中进行回流处理。 一种装置包括回流室，回流室的门，回流室中的能量源，以及耦合到该室的气体供应设备。 门可操作以将环境包围在回流室中。 能量源可操作以增加回流室中环境中的温度。 气体供应设备可操作以向回流室提供气体。

公开(公告)号：US20150228614A1

公开(公告)日：2015-08-13

申请号：US14177348

申请日：2014-02-11

Applicant: International Business Machines Corporation

Inventor： MARCUS E INTERRANTE ,  Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L23/498 ,  B23K3/06 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/81 ,  B23K3/0623 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75983 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/2064 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/0665 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2221/68381 ,  H01L2224/83 ,  H01L2924/00

Abstract: An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.

Abstract translation: 包含第一组焊球的插入器结构放置在真空分配板附近，真空分配板具有平面接触表面和位于其中的多个开口。 然后通过真空分配板中的开口施加真空，使得第一组焊球悬挂在多个开口内，并且插入件结构符合真空分配板的平面接触表面。 包含第二组焊球的半导体芯片被固定到中介层结构的表面。 然后将衬底与包含第一组焊球的内插器结构的表面接触，然后可以进行焊料回流和底部填充处理。 使用上述真空分配板基本上消除了内插器结构的翘曲。

公开(公告)号：US08853002B2

公开(公告)日：2014-10-07

申请号：US13734644

申请日：2013-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiu-Jen Lin ,  Ai-Tee Ang ,  Yu-Jen Tseng ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/10152 ,  H01L2224/1132 ,  H01L2224/11422 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11602 ,  H01L2224/1161 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13387 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75101 ,  H01L2224/75253 ,  H01L2224/7526 ,  H01L2224/75263 ,  H01L2224/75266 ,  H01L2224/7598 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/81024 ,  H01L2224/81222 ,  H01L2224/81224 ,  H01L2224/8123 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0541 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

Abstract translation: 组装金属凸块的方法。 在一个实施例中，一种方法包括提供具有多个导电端子的集成电路管芯; 沉积焊料以在导电端子上形成焊料沉积; 提供在用于接收所述集成电路裸片的表面上具有管芯附着区域的衬底，所述衬底具有形成在所述管芯附着区域中的多个导电迹线; 对准集成电路管芯和衬底并使多个导电端子和导电迹线接触，使得焊料沉积物物理接触导电迹线; 并且将集成电路管芯和导电端子选择性地加热到足以使焊料沉积物熔化和回流的温度，在衬底上的导电迹线和集成电路管芯上的导电端子之间形成焊接连接​​。 公开了用于选择性加热的各种能量源。

公开(公告)号：US20140193952A1

公开(公告)日：2014-07-10

申请号：US13734644

申请日：2013-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiu-Jen Lin ,  Ai-Tee Ang ,  Yu-Jen Tseng ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/10152 ,  H01L2224/1132 ,  H01L2224/11422 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11602 ,  H01L2224/1161 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13387 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75101 ,  H01L2224/75253 ,  H01L2224/7526 ,  H01L2224/75263 ,  H01L2224/75266 ,  H01L2224/7598 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/81024 ,  H01L2224/81222 ,  H01L2224/81224 ,  H01L2224/8123 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0541 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

Abstract translation: 组装金属凸块的方法。 在一个实施例中，一种方法包括提供具有多个导电端子的集成电路管芯; 沉积焊料以在导电端子上形成焊料沉积; 提供在用于接收所述集成电路裸片的表面上具有管芯附着区域的衬底，所述衬底具有形成在所述管芯附着区域中的多个导电迹线; 对准集成电路管芯和衬底并使多个导电端子和导电迹线接触，使得焊料沉积物物理接触导电迹线; 并且将集成电路管芯和导电端子选择性地加热到足以使焊料沉积物熔化和回流的温度，在衬底上的导电迹线和集成电路管芯上的导电端子之间形成焊接连接​​。 公开了用于选择性加热的各种能量源。