公开(公告)号：US12063735B2

公开(公告)日：2024-08-13

申请号：US18353295

申请日：2023-07-17

Applicant: Texas Instruments Incorporated

Inventor： Snehamay Sinha ,  Tapobrata Bandyopadhyay ,  Markarand Ramkrishna Kulkarni

IPC: H05K1/00 ,  H01L21/02 ,  H01L23/06 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0221 ,  H01L21/02008 ,  H01L23/06 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/42

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

公开(公告)号：US20220015225A1

公开(公告)日：2022-01-13

申请号：US17483726

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Snehamay Sinha ,  Tapobrata Bandyopadhyay ,  Markarand Ramkrishna Kulkarni

IPC: H05K1/02 ,  H05K1/11 ,  H01L21/02 ,  H05K3/42 ,  H01L23/06

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

公开(公告)号：US20220223509A1

公开(公告)日：2022-07-14

申请号：US17707872

申请日：2022-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

IPC: H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

公开(公告)号：US11800636B2

公开(公告)日：2023-10-24

申请号：US17483726

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Snehamay Sinha ,  Tapobrata Bandyopadhyay ,  Markarand Ramkrishna Kulkarni

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H01L21/02 ,  H05K3/42 ,  H01L23/06

CPC classification number: H05K1/0221 ,  H01L21/02008 ,  H01L23/06 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/42

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

公开(公告)号：US11160163B2

公开(公告)日：2021-10-26

申请号：US15816667

申请日：2017-11-17

Applicant: Texas Instruments Incorporated

Inventor： Snehamay Sinha ,  Tapobrata Bandyopadhyay ,  Makarand Ramkrishna Kulkarni

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H01L21/02 ,  H05K3/42 ,  H01L23/06

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

公开(公告)号：US12021004B2

公开(公告)日：2024-06-25

申请号：US17510684

申请日：2021-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiep Xuan Nguyen ,  Jaimal Mallory Wiliamson ,  Arvin Nono Verdeflor ,  Snehamay Sinha

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/4817 ,  H01L21/565 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/16724

Abstract: An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.

公开(公告)号：US20220319950A1

公开(公告)日：2022-10-06

申请号：US17510684

申请日：2021-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiep Xuan Nguyen ,  Jaimal Mallory Wiliamson ,  Arvin Nono Verdeflor ,  Snehamay Sinha

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.

公开(公告)号：US11289412B2

公开(公告)日：2022-03-29

申请号：US16795873

申请日：2020-02-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

IPC: H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48 ,  H01L23/48

Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

公开(公告)号：US20230363083A1

公开(公告)日：2023-11-09

申请号：US18353295

申请日：2023-07-17

Applicant: Texas Instruments Incorporated

Inventor： Snehamay Sinha ,  Tapobrata Bandyopadhyay ,  Markarand Ramkrishna Kulkarni

IPC: H05K1/02 ,  H05K1/11 ,  H01L21/02 ,  H05K3/42 ,  H01L23/06

CPC classification number: H05K1/0221 ,  H05K1/115 ,  H01L21/02008 ,  H05K3/42 ,  H01L23/06 ,  H05K1/0222 ,  H05K1/0245

Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

公开(公告)号：US11804382B2

公开(公告)日：2023-10-31

申请号：US17707872

申请日：2022-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Snehamay Sinha

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/81815

Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.