公开(公告)号：US20150003490A1

公开(公告)日：2015-01-01

申请号：US13931799

申请日：2013-06-28

Applicant: Texas Instruments Incorporated

Inventor： Mikel K. Ash ,  Xiao Pu ,  Joonsung Park ,  Krishnaswamy Nagaraj

IPC: G01K15/00

CPC classification number: G01K15/005 ,  G01K7/01 ,  G01K2219/00

Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

Abstract translation: 温度传感器使用具有与绝对温度（PTAT）成比例的已知电压降特性的半导体器件。 可控电流源耦合到半导体器件，并且可操作地将具有值I（偏置）和I（偏压）的固定比率N的偏置电流顺序地注入到半导体器件中。 ΔΣ模数转换器（ADC）具有耦合到半导体器件的输入。 ΔΣADC被配置为通过将选择的偏置电流的有序序列重复地注入到半导体器件中来对半导体器件产生的电压对序列进行采样和积分。 选择的偏置电流的有序序列包括（N×I（偏置）; I（偏置））和（M×I（偏置）; M×N×I（偏置））的一次重复的M次重复。

公开(公告)号：US20140136138A1

公开(公告)日：2014-05-15

申请号：US13674941

申请日：2012-11-12

Applicant: TEXAS INSTRUMENTS, INCORPORATED

Inventor： Joonsung Park ,  Srinadh Madhavapeddi ,  Christopher Barr

IPC: G01R31/28 ,  G06F17/00

CPC classification number: G06F17/00 ,  G01N29/46 ,  G01R23/16 ,  G01R31/28 ,  G01R31/3172 ,  G01R31/31721 ,  G01R31/31727 ,  G06F11/2294 ,  G06F11/24 ,  G06F17/141

Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

Abstract translation: 计算设备使用递归离散傅里叶变换（RDFT）引擎来减少频率变换模块所需的时间，保存中间产品所需的存储器和/或用于测试的计算资源。 在一个实施例中，窗口功能与递归DFT功能同时整合和处理。 频率仓功率模块被配置为确定在各种递归水平下具有最大信号功率的频率组集合内的频率仓。

公开(公告)号：US20250141458A1

公开(公告)日：2025-05-01

申请号：US19004920

申请日：2024-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christy Leigh She ,  Joonsung Park ,  Krishnasawamy Nagaraj ,  Srinivasa Chakravarthy

IPC: H03M1/08

Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

公开(公告)号：US11387837B1

公开(公告)日：2022-07-12

申请号：US17137691

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Krishnaswamy Nagaraj ,  Joonsung Park

IPC: H03M1/00 ,  H03M1/46

Abstract: A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.

公开(公告)号：US09692445B1

公开(公告)日：2017-06-27

申请号：US15072837

申请日：2016-03-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brent Peterson ,  Joonsung Park ,  Krishnaswamy Nagaraj ,  Tyler Witt

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/30 ,  G06G7/26 ,  H03M3/50 ,  H03M7/3042

Abstract: A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.

公开(公告)号：US20160056831A1

公开(公告)日：2016-02-25

申请号：US14462916

申请日：2014-08-19

Applicant: Texas Instruments Incorporated

Inventor： Joonsung Park ,  Krishnaswamy Nagaraj ,  Mikel Ash

IPC: H03M1/20 ,  H03M1/46

CPC classification number: H03M1/20 ,  H03M1/162 ,  H03M1/38 ,  H03M1/462

Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

Abstract translation: 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。