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公开(公告)号：US11740106B2
公开(公告)日：2023-08-29
申请号：US18054949
申请日：2022-11-14
CPC分类号： G01D5/245 , H02K11/21 , H03M1/12 , H03M1/66 , G01D5/02 , G01D5/3473 , G01D5/34753 , H03M1/22
摘要： In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.
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公开(公告)号：US20240322831A1
公开(公告)日：2024-09-26
申请号：US18732693
申请日：2024-06-04
IPC分类号： H03L7/24 , G06F1/08 , G06F1/3296 , H03M1/12
CPC分类号： H03L7/24 , G06F1/08 , G06F1/3296 , H03M1/1245
摘要： Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.
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公开(公告)号：US11073409B2
公开(公告)日：2021-07-27
申请号：US16211374
申请日：2018-12-06
摘要： In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.
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公开(公告)号：US12034449B2
公开(公告)日：2024-07-09
申请号：US17977263
申请日：2022-10-31
IPC分类号： H03L7/24 , G06F1/08 , G06F1/3296 , H03M1/12
CPC分类号： H03L7/24 , G06F1/08 , G06F1/3296 , H03M1/1245
摘要： Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.
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公开(公告)号：US20230299778A1
公开(公告)日：2023-09-21
申请号：US17977263
申请日：2022-10-31
IPC分类号： H03L7/24 , H03M1/12 , G06F1/08 , G06F1/3296
CPC分类号： H03L7/24 , G06F1/08 , G06F1/3296 , H03M1/1245
摘要： Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.
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公开(公告)号：US12119826B2
公开(公告)日：2024-10-15
申请号：US17849417
申请日：2022-06-24
IPC分类号： H03K5/00 , G06F1/06 , G06F11/263 , H03K21/02
CPC分类号： H03K5/00006 , G06F1/06 , G06F11/263 , H03K21/02
摘要： An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.
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公开(公告)号：US20240187015A1
公开(公告)日：2024-06-06
申请号：US18437510
申请日：2024-02-09
CPC分类号： H03M1/12 , H03M1/00 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F13/00 , G06F13/28 , G06F2213/28
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
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8.发明公开公开(公告)号：US20240146323A1
公开(公告)日：2024-05-02
申请号：US17976369
申请日：2022-10-28
IPC分类号： H03M1/08
CPC分类号： H03M1/08
摘要： Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.
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公开(公告)号：US11942962B2
公开(公告)日：2024-03-26
申请号：US17691606
申请日：2022-03-10
CPC分类号： H03M1/12 , H03M1/00 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F13/00 , G06F13/28 , G06F2213/28
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
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公开(公告)号：US20230129042A1
公开(公告)日：2023-04-27
申请号：US17691606
申请日：2022-03-10
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
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