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    Adaptive clocking for analog-to-digital conversion
    2.
    发明授权
    Adaptive clocking for analog-to-digital conversion 有权
    适用于模数转换的时钟

    公开(公告)号：US09197238B1

    公开(公告)日：2015-11-24

    申请号：US14478513

    申请日：2014-09-05

    Applicant: Texas Instruments Incorporated

    Inventor： Krishnaswamy Nagaraj ,  Joonsung Park ,  Ajay Kumar

    IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12 ,  H03L7/08

    CPC classification number: H03L7/0991 ,  H03L7/08 ,  H03L7/083 ,  H03L7/085 ,  H03M1/0624 ,  H03M1/1009 ,  H03M1/1255 ,  H03M1/38

    Abstract: An analog-to-digital conversion system and method includes, for example, a comparator for sampling an analogy quantity during a sampling period and for performing a series of bit-wise conversions on the sampled analog sample during a conversion period, where each bit-wise conversion occurs during a respective bit-wise conversion cycle in which successive bits of a sample are successively determined during a respective bit conversion cycle and in which a predetermined number of bit-wise conversions are to be performed. A clock generator is arranged for generating a clock signal for clocking the converter during the conversion period, wherein each bit conversion cycle includes a reset period having a first length and an amplification period having a second length, wherein one of the first and second lengths is dynamically selected.

    Abstract translation: 模数转换系统和方法包括例如比较器，用于在采样周期期间对类比数量进行采样，并且在转换周期期间对采样的模拟采样执行一系列逐位转换，其中每个位 - 在相应的逐位转换周期期间发生明智转换，其中在相应的位转换周期期间连续地确定采样的连续位，并且将执行预定数量的逐位转换。 时钟发生器被布置用于在转换周期期间产生用于对转换器进行时钟的时钟信号，其中每个位转换周期包括具有第一长度的复位周期和具有第二长度的放大周期，其中第一和第二长度中的一个是 动态选择。

    Autoconfigurable Phase-Locked Loop Which Automatically Maintains a Constant Damping Factor and Adjusts the Loop Bandwidth to a Constant Ratio of the Reference Frequency
    6.
    发明申请
    Autoconfigurable Phase-Locked Loop Which Automatically Maintains a Constant Damping Factor and Adjusts the Loop Bandwidth to a Constant Ratio of the Reference Frequency 审中-公开
    自动配置锁相环，自动维持恒定阻尼系数，并将环路带宽调整到参考频率的恒定比

    公开(公告)号：US20160301418A1

    公开(公告)日：2016-10-13

    申请号：US15188481

    申请日：2016-06-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ajay Kumar ,  Krishnaswamy Nagaraj ,  Joonsung Park

    IPC: H03L7/107 ,  H03L7/18 ,  H03L7/087

    CPC classification number: H03L7/107 ,  H03L7/06 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/1072 ,  H03L7/1075 ,  H03L7/18 ,  H03L2207/04

    Abstract: A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.

    Abstract translation: 锁相环（PLL）包括被编程为自动产生一组控制信号以选择电荷泵电流并且积分电容值以自动调整PLL的环路带宽的状态机。 电荷泵DAC产生由状态机控制信号控制的电荷泵电流。 积分器集成了电荷泵输出电流，以产生集成的电荷泵输出信号。 积分器具有通过来自状态机的控制信号可切换地选择的多个电容器，以产生积分电容值。 压控振荡器（VCO）响应于集成的电荷泵输出信号产生PLL输出频率。

    Resistance and offset cancellation in a remote-junction temperature sensor
    7.
    发明授权
    Resistance and offset cancellation in a remote-junction temperature sensor 有权
    远程结温传感器中的电阻和偏移消除

    公开(公告)号：US09395253B2

    公开(公告)日：2016-07-19

    申请号：US13931799

    申请日：2013-06-28

    Applicant: Texas Instruments Incorporated

    Inventor： Mikel K. Ash ,  Xiao Pu ,  Joonsung Park ,  Krishnaswamy Nagaraj

    IPC: G01K15/00 ,  G01K7/00 ,  H03M3/00 ,  G01K7/01

    CPC classification number: G01K15/005 ,  G01K7/01 ,  G01K2219/00

    Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

    Abstract translation: 温度传感器使用具有与绝对温度（PTAT）成比例的已知电压降特性的半导体器件。 可控电流源耦合到半导体器件，并且可操作地将具有值I（偏置）和I（偏压）的固定比率N的偏置电流顺序地注入到半导体器件中。 ΔΣ模数转换器（ADC）具有耦合到半导体器件的输入。 ΔΣADC被配置为通过将选择的偏置电流的有序序列重复地注入到半导体器件中来对半导体器件产生的电压对序列进行采样和积分。 选择的偏置电流的有序序列包括（N×I（偏置）; I（偏置））和（M×I（偏置）; M×N×I（偏置））的一次重复的M次重复。

    Enhanced resolution successive-approximation register analog-to-digital converter and method
    9.
    发明授权
    Enhanced resolution successive-approximation register analog-to-digital converter and method 有权
    增强分辨率逐次逼近寄存器模数转换器和方法

    公开(公告)号：US09252800B1

    公开(公告)日：2016-02-02

    申请号：US14462916

    申请日：2014-08-19

    Applicant: Texas Instruments Incorporated

    Inventor： Joonsung Park ,  Krishnaswamy Nagaraj ,  Mikel Ash

    IPC: H03M1/38 ,  H03M1/20 ,  H03M1/46

    CPC classification number: H03M1/20 ,  H03M1/162 ,  H03M1/38 ,  H03M1/462

    Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

    Abstract translation: 提供了增强分辨率逐次逼近寄存器（SAR）模数转换器（ADC），其包括数模转换器（DAC），比较器和增强分辨率SAR控制逻辑。 DAC包括配置为将M位数字输入转换为模拟输出的模拟电路。 比较器包括多个耦合电容器。 增强分辨率SAR控制逻辑被配置为产生输入电压的M位近似值，并将剩余电压存储在至少一个耦合电容器中。 残余电压表示输入电压和输入电压的M位近似之间的差。 增强分辨率SAR控制逻辑还被配置为基于存储的残留电压来产生输入电压的N位近似，其中N> M。

    Analog-to-digital convertors positioned on a single semiconductor die
    10.
    发明授权
    Analog-to-digital convertors positioned on a single semiconductor die 有权

    公开(公告)号：US12212331B2

    公开(公告)日：2025-01-28

    申请号：US17976369

    申请日：2022-10-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Christy Leigh She ,  Joonsung Park ,  Krishnasawamy Nagaraj ,  Srinivasa Chakravarthy

    IPC: H03M1/06 ,  H03M1/08

    Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

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