-
公开(公告)号：US11047746B2
公开(公告)日：2021-06-29
申请号：US16852659
申请日：2020-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Byron Jon Roderick Shulver
Abstract: A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.
-
公开(公告)号：US10534045B2
公开(公告)日：2020-01-14
申请号：US15709866
申请日：2017-09-20
Applicant: Texas Instruments Incorporated
Inventor： Keith Ryan Green , Byron Jon Roderick Shulver , Iouri Mirgorodski
Abstract: A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.
-
公开(公告)号：US20190319068A1
公开(公告)日：2019-10-17
申请号：US16453468
申请日：2019-06-26
Applicant: Texas Instruments Incorporated
Inventor： Keith Ryan Green , Rajni J. Aggarwal , Ajit Sharma
Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.
-
公开(公告)号：US10396122B2
公开(公告)日：2019-08-27
申请号：US15639327
申请日：2017-06-30
Applicant: Texas Instruments Incorporated
Inventor： Keith Ryan Green , Rajni J. Aggarwal , Ajit Sharma
Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.
-
公开(公告)号：US20190036012A1
公开(公告)日：2019-01-31
申请号：US16147007
申请日：2018-09-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , louri Mirgorodski
CPC classification number: H01L43/06 , H01L22/30 , H01L43/065 , H01L43/14
Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.
-
Patent Agency Ranking
公开(公告)号：US09893119B2
公开(公告)日：2018-02-13
申请号：US15070413
申请日：2016-03-15
Applicant: Texas Instruments Incorporated
Inventor： Dok Won Lee , William David French , Keith Ryan Green
CPC classification number: H01L27/22 , H01L43/04 , H01L43/065 , H01L43/14
Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.
-
公开(公告)号：US20240329164A1
公开(公告)日：2024-10-03
申请号：US18193099
申请日：2023-03-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Dok Won Lee , Keith Ryan Green , Fanping Sui , Charles Parkhurst
CPC classification number: G01R33/077 , G01R33/0011 , H10N52/01 , H10N52/80
Abstract: The present disclosure generally relates to magnetic field sensors with magnetic flux concentrators, and more particularly, to Hall sensors (which may be vertical or in-plane field Hall sensors) with magnetic flux concentrators. In an example, a sensor device includes a semiconductor die, a first magnetic flux concentrator, and a second magnetic flux concentrator. The semiconductor die includes a semiconductor substrate and an interconnect structure. The semiconductor substrate includes a Hall sensor in a semiconductor material. The interconnect structure is over the semiconductor substrate. The first magnetic flux concentrator is over the semiconductor die. The second magnetic flux concentrator is over the semiconductor die. At least part of the Hall sensor is laterally between the first magnetic flux concentrator and the second magnetic flux concentrator.
-
公开(公告)号：US12013419B2
公开(公告)日：2024-06-18
申请号：US17871873
申请日：2022-07-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Dok Won Lee , Jo Bito , Keith Ryan Green
CPC classification number: G01R15/207 , G01R15/202 , H01L23/49586 , H10N52/00 , H10N52/80 , H10B61/00 , H10N59/00
Abstract: In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.
-
公开(公告)号：US11782102B2
公开(公告)日：2023-10-10
申请号：US17508706
申请日：2021-10-22
Applicant: Texas Instruments Incorporated
Inventor： Keith Ryan Green , Erika Lynn Mazotti , William David French , Ricky Alan Jackson
CPC classification number: G01R33/072 , G01R33/0052 , G01R33/077 , H10N52/01 , H10N52/101 , H10N52/80
Abstract: A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.
-
公开(公告)号：US20220075009A1
公开(公告)日：2022-03-10
申请号：US17015327
申请日：2020-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Tony Ray Larson
Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.022 seconds)
