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11.发明申请公开(公告)号：US20170033552A1
公开(公告)日：2017-02-02
申请号：US15225462
申请日：2016-08-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sualp Aras , Adam Quirk , Md. Abidur Rahman
Abstract: A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.
Abstract translation: 具有用于感测参考电流的输入和用于感测参考电压的输入的电路保护系统。 该系统还具有用于响应于参考电流和参考电压确定估计能量的电路和用于响应于所估计的能量超过阈值产生控制信号的电路。
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12.发明申请Circuit Reliability Improvement By Detecting and Mitigating High Voltage Transient Event At Supply 审中-公开通过检测和减轻供电时的高压瞬变事件，可靠性提高电路可靠性公开(公告)号：US20170033551A1
公开(公告)日：2017-02-02
申请号：US15225478
申请日：2016-08-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung J. Kim , Md. Abidur Rahman , Sualp Aras
Abstract: A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.
Abstract translation: 一种具有用于输出第一电压的第一电压源和用于输出第二电压的第二电压源的电路可靠性系统。 该系统还包括：（i）至少一个节点，用于响应于第一电压和第二电压提供电位; （ii）用于检测超过阈值的第一电压的监控电路; 以及（iii）禁用电路，用于响应于所述监视电路检测到所述第一电压超过阈值而禁用所述第二电压供应。
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公开(公告)号：US11218147B2
公开(公告)日：2022-01-04
申请号：US17018458
申请日：2020-09-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Md. Abidur Rahman , Adam Quirk , Stephen Nortman , Sualp Aras
IPC: H02H3/00 , H03K17/082 , H02H3/06 , H02H5/04 , H03K17/08
Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.
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公开(公告)号：US10404056B2
公开(公告)日：2019-09-03
申请号：US15225462
申请日：2016-08-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sualp Aras , Adam Quirk , Md. Abidur Rahman
Abstract: A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.
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公开(公告)号：US10386876B2
公开(公告)日：2019-08-20
申请号：US15231472
申请日：2016-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Md. Abidur Rahman , Sualp Aras , Tri Cao Nguyen
IPC: G05F1/573 , G05F1/571 , G01R31/28 , H02H3/08 , H02H9/02 , H02H3/087 , G05F1/569 , H02H3/20 , H02H3/00
Abstract: A circuit protective system. The system has: (i) an input for sensing an operational voltage responsive to a current flowing through a transistor; (ii) circuitry for applying a forced voltage at the input; (iii) voltage-to-current conversion circuitry for outputting a reference current in response to the forced voltage at the input; (iv) circuitry for providing a reference trim current in response to a trim indicator; and (v) comparison circuitry for outputting a limit signal in response to a comparison of the reference current and the reference trim current.
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Patent Agency Ranking
公开(公告)号：US20180287602A1
公开(公告)日：2018-10-04
申请号：US16001518
申请日：2018-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K17/082 , H01L23/525 , H03K17/687 , G01R19/00
CPC classification number: H03K17/0822 , G01R19/0092 , H01L23/5256 , H03K17/687 , H03K2217/0027 , H03K2217/0054
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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17.发明申请Methods and Apparatus for Compensation and Current Spreading Correction in Shared Drain Multi-Channel Load Switch 审中-公开在共享排水多通道负载开关中的补偿和电流扩展校正的方法和装置公开(公告)号：US20170030948A1
公开(公告)日：2017-02-02
申请号：US15211450
申请日：2016-07-15
Applicant: Texas Instruments Incorporated
Inventor： David J. Baldwin , Hector X. Roman , Md. Abidur Rahman
IPC: G01R19/10 , H01L29/417 , H01L27/088
CPC classification number: H01L27/088 , G01R19/0092 , H01L29/7802 , H03K17/08 , H03K17/145
Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.
Abstract translation: 所描述的示例实施例包括具有形成在半导体衬底中的第一FET的第一沟道区的集成电路，该衬底提供与漏极的接触。 第二沟道区域包括形成在半导体衬底中的第二FET。 引导FET以电流镜配置耦合到第一FET。 第三FET具有与第一和第二FET相反的导电性并耦合到引导FET的源极。 运算放大器包括耦合到第三FET的栅极的输出。 来自第二FET的漏极和引导FET的源极的信号耦合到运算放大器的反相输入。 来自第一FET的源极和第一FET耦合的漏极到运算放大器的非反相输入端的信号。 公开了方法和附加装置。
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公开(公告)号：US10361695B2
公开(公告)日：2019-07-23
申请号：US16001518
申请日：2018-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K3/00 , H03K17/082 , G01R19/00 , H01L23/525 , H03K17/687
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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19.发明授权公开(公告)号：US10326268B2
公开(公告)日：2019-06-18
申请号：US15225478
申请日：2016-08-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung J. Kim , Md. Abidur Rahman , Sualp Aras
Abstract: A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.
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公开(公告)号：US20180123578A1
公开(公告)日：2018-05-03
申请号：US15341205
申请日：2016-11-02
Applicant: Texas Instruments Incorporated
Inventor： Ankur Chauhan , Sudheer Prasad , Md. Abidur Rahman , Subrato Roy
IPC: H03K17/082 , H03K17/687 , H01L23/525 , G01R19/00
CPC classification number: H03K17/0822 , G01R19/0092 , H01L23/5256 , H03K17/687 , H03K2217/0027 , H03K2217/0054
Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
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