公开(公告)号：US20140252367A1

公开(公告)日：2014-09-11

申请号：US13789949

申请日：2013-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L27/088 ,  H01L21/8236

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在同一个硅衬底上。

公开(公告)号：US20140042452A1

公开(公告)日：2014-02-13

申请号：US13886410

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/20 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66477 ,  H01L29/7786

Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.

Abstract translation: 半导体器件包括在增强型GaN FET的栅极节点和半导体器件的栅极端子之间串联电耦合的耗尽型GaN FET的增强型GaN FET。 耗尽型GaN FET的栅极节点电耦合到增强型GaNFET的源极节点。 所述增强型GaN FET的源节点电耦合到半导体器件的源极端子，增强型GaNFET的漏极节点电耦合到所述半导体器件的漏极端子，并且耗尽模式的漏极节点 GaN FET电耦合到半导体器件的栅极端子。

公开(公告)号：US20200303535A1

公开(公告)日：2020-09-24

申请号：US16895111

申请日：2020-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20170098702A1

公开(公告)日：2017-04-06

申请号：US15380280

申请日：2016-12-15

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/778 ,  H01L49/02 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20 ,  H01L27/06

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

公开(公告)号：US20150287641A1

公开(公告)日：2015-10-08

申请号：US14745749

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L21/8236 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8234

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US20150243742A1

公开(公告)日：2015-08-27

申请号：US14706595

申请日：2015-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US20140374766A1

公开(公告)日：2014-12-25

申请号：US13922352

申请日：2013-06-20

Applicant: Texas Instruments Incorporated

Inventor： Sandeep R. BAHL ,  Matthew SENESKY ,  Naveen TIPIRNENI ,  David I. ANDERSON ,  Sameer PENDHARKAR

IPC: H01L27/06 ,  H01L29/20

CPC classification number: H01L27/0629 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/48465

Abstract: A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.

Abstract translation: 半导体器件包括形成在非绝缘衬底上的双向GaN FET。 所述半导体器件还包括连接在所述衬底和所述双向GaN FET的第一源极/漏极节点之间的第一电夹以及连接在所述衬底与所述双向GaN FET的第二源极/漏极节点之间的第二电夹。 第一钳位和第二钳位被配置为在施加的偏压的较低电压电平下将衬底偏置到第一源极/漏极节点，并在相关钳位的偏移电压内将施加的偏压施加到第二源极/漏极节点。