公开(公告)号：US08643099B2

公开(公告)日：2014-02-04

申请号：US13922381

申请日：2013-06-20

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

Abstract translation: 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US20170264289A1

公开(公告)日：2017-09-14

申请号：US15067928

申请日：2016-03-11

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L27/092

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09087708B2

公开(公告)日：2015-07-21

申请号：US13960472

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： John Lin ,  Philip L. Hower

IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L29/0646 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/092

Abstract: An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.

Abstract translation: 集成电路（IC）包括具有p型半导体表面的衬底。 第一nwell包括围绕形成在半导体表面中的第一多个半导体器件的区域，其具有在其下的第一n埋层（NBL）。 形成在半导体表面中的垂直二极管围绕包括在浮动NBL环顶部的孔的第一nwell。 形成在半导体表面中的第二nwell包括围绕浮动NBL环的区域，并围绕其下具有第二NBL的第二多个半导体器件。

公开(公告)号：US10937905B2

公开(公告)日：2021-03-02

申请号：US14286202

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  Sameer P. Pendharkar ,  John Lin ,  Guru Mathur ,  Scott Balster ,  Victor Sinow

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

公开(公告)号：US10601422B2

公开(公告)日：2020-03-24

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/10 ,  H03K17/12 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US20180108729A1

公开(公告)日：2018-04-19

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US20180097517A1

公开(公告)日：2018-04-05

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09349933B2

公开(公告)日：2016-05-24

申请号：US14180744

申请日：2014-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Barry Jon Male ,  Philip L. Hower

IPC: H01L35/30 ,  H01L23/38 ,  H01L35/32

CPC classification number: H01L35/30 ,  H01L23/38 ,  H01L27/16 ,  H01L35/22 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract translation: 公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。 侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。 侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。 当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。 热功率流过垂直管道到横向热电元件，产生电位。 电位可以施加到IC中的元件或电路。 热电装置可以集成到IC中而不增加制造成本或复杂性。

公开(公告)号：US20140216517A1

公开(公告)日：2014-08-07

申请号：US14180744

申请日：2014-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Barry Jon Male ,  Philip L. Hower

IPC: H01L35/30

CPC classification number: H01L35/30 ,  H01L23/38 ,  H01L27/16 ,  H01L35/22 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract translation: 公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。 侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。 侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。 当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。 热功率流过垂直管道到横向热电元件，产生电位。 电位可以施加到IC中的元件或电路。 热电装置可以集成到IC中而不增加制造成本或复杂性。