公开(公告)号：US11482613B2

公开(公告)日：2022-10-25

申请号：US16272025

申请日：2019-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

公开(公告)号：US10319809B2

公开(公告)日：2019-06-11

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09876071B2

公开(公告)日：2018-01-23

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09608088B2

公开(公告)日：2017-03-28

申请号：US14284696

申请日：2014-05-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/66681 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7816

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

公开(公告)号：US20160254346A1

公开(公告)日：2016-09-01

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract translation: 半导体器件包含在漏极漂移区域上具有横向n型漏极漂移区域和p型RESURF区域的LDNMOS晶体管。 RESURF区域延伸到半导体器件的衬底的顶表面。 半导体器件包括电耦合在RESURF区域和LDNMOS晶体管的低电压节点之间的分流器。 分路可以是RESURF层和LDNMOS晶体管的主体之间的衬底中的p型注入层，并且可以与RESURF层同时注入。 分流器可以穿过漏极漂移区域中的从RESURF层到漏极漂移区域下方的衬底的开口。 分路可以包括包括触点和金属互连线的金属互连元件。

公开(公告)号：US10937905B2

公开(公告)日：2021-03-02

申请号：US14286202

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  Sameer P. Pendharkar ,  John Lin ,  Guru Mathur ,  Scott Balster ,  Victor Sinow

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

公开(公告)号：US10205001B2

公开(公告)日：2019-02-12

申请号：US15226036

申请日：2016-08-02

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

公开(公告)号：US20180108729A1

公开(公告)日：2018-04-19

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09087708B2

公开(公告)日：2015-07-21

申请号：US13960472

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： John Lin ,  Philip L. Hower

IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L29/0646 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/092

Abstract: An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.

Abstract translation: 集成电路（IC）包括具有p型半导体表面的衬底。 第一nwell包括围绕形成在半导体表面中的第一多个半导体器件的区域，其具有在其下的第一n埋层（NBL）。 形成在半导体表面中的垂直二极管围绕包括在浮动NBL环顶部的孔的第一nwell。 形成在半导体表面中的第二nwell包括围绕浮动NBL环的区域，并围绕其下具有第二NBL的第二多个半导体器件。