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    Reducing transients for multiphase power regulators
    12.
    发明授权
    Reducing transients for multiphase power regulators 有权

    公开(公告)号：US11811326B2

    公开(公告)日：2023-11-07

    申请号：US17682747

    申请日：2022-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naman Bafna ,  Cheng Wei Chen ,  Preetam Charan Anand Tadeparthy ,  Sreelakshmi Suresh ,  Ammineni Balaji

    IPC: H02M3/158 ,  H02M1/00 ,  H02M3/156

    CPC classification number: H02M3/1586 ,  H02M1/0003 ,  H02M3/1584 ,  H02M3/1566

    Abstract: An example circuit includes a loop controller having current phase inputs, a feedback input, a control loop output and a transient event output. The feedback input is adapted to be coupled to an output terminal of a multi-phase power stage. A PWM circuit has a blanking input, a control input and a PWM output, the control input coupled to the control loop output. A phase management circuit has a transient detect input, a PWM input, a blanking output and phase outputs. The transient detect input is coupled to the transient event output. The PWM input is coupled to the PWM output and the blanking output is coupled to the blanking input. Each of the phase outputs is adapted to be coupled to a respective phase of the multi-phase power stage. The phase management circuit is configured to provide a blanking control signal representative of a variable blanking time.

    Power Regulator with Variable Rate Integrator
    14.
    发明申请
    Power Regulator with Variable Rate Integrator 有权

    公开(公告)号：US20230079601A1

    公开(公告)日：2023-03-16

    申请号：US17489782

    申请日：2021-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Naman Bafna ,  Preetam Charan Anand Tadeparthy ,  Ammineni Balaji ,  Sreelakshmi Suresh

    IPC: H02M3/158 ,  H02M1/00

    Abstract: In described examples of a system having a proportional-integral control module, an error signal is produced that is indicative of a difference between a reference signal and an output signal. An integral control signal is produced by integrating the error signal using an integrator time constant value. During a steady state condition, a first integrator time constant value is used. When an undershoot in the output signal is detected, the integrator time constant value is increased to a second time constant value that is larger than the first integrator time constant value during the undershoot condition. The integrator time constant value is reduced to a third integrator time constant value that is less than the first integrator time constant value during a period following the undershoot condition.

    Comparator architecture for reduced delay and lower static current
    15.
    发明授权
    Comparator architecture for reduced delay and lower static current 有权

    公开(公告)号：US11595033B2

    公开(公告)日：2023-02-28

    申请号：US17515018

    申请日：2021-10-29

    Applicant: Texas Instruments Incorporated

    Inventor： Vishnuvardhan Reddy Jaladanki ,  Preetam Charan Anand Tadeparthy

    IPC: H03K5/24

    Abstract: Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.

    ARCHITECTURE TO MITIGATE OVERSHOOT/UNDERSHOOT IN A VOLTAGE REGULATOR
    16.
    发明申请
    ARCHITECTURE TO MITIGATE OVERSHOOT/UNDERSHOOT IN A VOLTAGE REGULATOR 有权

    公开(公告)号：US20220209648A1

    公开(公告)日：2022-06-30

    申请号：US17137446

    申请日：2020-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Venkatesh Wadeyar ,  Vikas Lakhanpal ,  Preetam Charan Anand Tadeparthy

    IPC: H02M1/32 ,  G06F1/28

    Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.

    COMPARATOR ARCHITECTURE FOR REDUCED DELAY AND LOWER STATIC CURRENT
    17.
    发明申请
    COMPARATOR ARCHITECTURE FOR REDUCED DELAY AND LOWER STATIC CURRENT 有权

    公开(公告)号：US20220166419A1

    公开(公告)日：2022-05-26

    申请号：US17515018

    申请日：2021-10-29

    Applicant: Texas Instruments Incorporated

    Inventor： Vishnuvardhan Reddy Jaladanki ,  Preetam Charan Anand Tadeparthy

    IPC: H03K5/24

    Abstract: Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.

    METHODS AND APPARATUS TO CALIBRATE MULTIPHASE BUCK REGULATORS
    19.
    发明公开
    METHODS AND APPARATUS TO CALIBRATE MULTIPHASE BUCK REGULATORS 审中-公开

    公开(公告)号：US20240213880A1

    公开(公告)日：2024-06-27

    申请号：US18140418

    申请日：2023-04-27

    Applicant: Texas Instruments Incorporated

    Inventor： Vikas Lakhanpal ,  Preetam Charan Anand Tadeparthy ,  Sreelakshmi S ,  Mayank Jain ,  Charan Hemanth Kumar

    IPC: H02M3/158

    CPC classification number: H02M3/1586

    Abstract: An example non-transitory machine-readable storage medium includes instructions that, when executed, configure processor circuitry to at least: determine a first delay corresponding to an amount of time for a first pulse to reach first phase circuitry; determine a second delay corresponding to an amount of time for a second pulse to reach second phase circuitry; determine a third delay corresponding to an amount of time for a third pulse to reach third phase circuitry, wherein one or more of the first phase circuitry, the second phase circuitry, and the third phase circuitry are located a non-uniform distance from the processor circuitry; and transmit, based on the delays, the pulses to the respective phase circuitry such that a first time period between the first pulse and the second pulse is equal to a second time period between the second pulse and the third pulse.

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