公开(公告)号：US20230221959A1

公开(公告)日：2023-07-13

申请号：US18174715

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/30152 ,  G06F9/4843 ,  G06F9/3851

Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

公开(公告)号：US11593110B2

公开(公告)日：2023-02-28

申请号：US17143989

申请日：2021-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

公开(公告)号：US20220206065A1

公开(公告)日：2022-06-30

申请号：US17138529

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K3/037 ,  H03K19/003 ,  H03K5/24

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US11474151B2

公开(公告)日：2022-10-18

申请号：US17138529

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: H03K3/00 ,  G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US09645964B2

公开(公告)日：2017-05-09

申请号：US14695595

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  G06F11/10

CPC classification number: G06F13/4221 ,  G06F11/1008 ,  G06F11/1044 ,  G06F13/00 ,  G06F13/364

Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

公开(公告)号：US20150227488A1

公开(公告)日：2015-08-13

申请号：US14695595

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi

IPC: G06F13/42 ,  G06F11/10

CPC classification number: G06F13/4221 ,  G06F11/1008 ,  G06F11/1044 ,  G06F13/00 ,  G06F13/364

Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

Abstract translation: 管道通信系统包括被配置为彼此通信的主站和多个从站。 多个从站中的每一个包括存储器，并且被配置为产生第一就绪信号和第二就绪信号。 第一就绪信号被配置为仅提供给主机，并且第二就绪信号被配置为仅被提供给多个从机中的每一个。 第二就绪信号是独立于多个从机中的每一个中的错误检查产生的。

公开(公告)号：US20140372648A1

公开(公告)日：2014-12-18

申请号：US14306970

申请日：2014-06-17

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi

IPC: G06F13/37

CPC classification number: G06F13/37 ,  G06F13/1657

Abstract: A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

Abstract translation: 多主机芯片系统（SoC）包括多个主机，包括第一主机和第二主机，每个主机被配置为产生一个请求。 多主机SoC中的下一状态发生器被配置为响应于请求和循环指针的当前状态生成循环指针的下一状态。 循环指针被配置为响应于循环指针的当前状态而产生使能信号以使能第一主控的优先级编码器。 此外，生成循环指针的下一状态使得对于第一主机保持优先级，直到存在来自第二主机的请求。

公开(公告)号：US20130043905A1

公开(公告)日：2013-02-21

申请号：US13657142

申请日：2012-10-22

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi

IPC: H03K19/096

CPC classification number: H03K5/19 ,  G06F1/08 ,  H03K5/1252

Abstract: A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

Abstract translation: 无毛刺时钟切换电路包括第一使能同步逻辑，其响应于来自第一使能生成逻辑的第一使能而产生第一时钟使能。 时钟切换电路包括第二使能同步逻辑，其响应于来自第二使能产生逻辑的第二使能而产生第二时钟使能。 如果第二使能是逻辑高，逻辑门耦合到第二使能同步逻辑的输出，其选择第二时钟信号作为逻辑门输出。 优先多路复用器接收第一时钟信号，第一使能和逻辑门输出。 多路复用器被配置为如果第一使能是逻辑高，则选择第一时钟信号作为时钟输出，而与逻辑门输出无关。

公开(公告)号：US20250021656A1

公开(公告)日：2025-01-16

申请号：US18771795

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/60

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges, a logic circuit, access protection registers (APRs), ZONE debug permission registers, and a processor coupled to the memory. Each APR stores memory access permissions for an associated memory range. Each ZONE debug permission register stores debug permissions for a ZONE. Each ZONE is associated with a subset of the APRs so that each APR is associated with one ZONE. The processor executes a debug instruction to control the circuit device as follows. An APR associated with a memory address in the debug instruction provides a first permission to a first logic circuit input. The ZONE debug permission registers provide a second permission responsive to a credential to a second logic circuit input. The processor performs a debug action responsive to the debug instruction and a logic circuit output.

公开(公告)号：US20250021494A1

公开(公告)日：2025-01-16

申请号：US18771733

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F12/14 ,  G06F9/38

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges and a processor device coupled to the memory. The processor device is configured to fetch programmable instructions from the memory, and configured to determine memory access and execution permissions for the programmable instructions. Permissions are determined responsive to a set of a set of access protection registers (APRs) and a set of LINKs. The APRs each specify permissions for a respective associated memory range. The LINKs are each associated with a respective subset of the APRs. Each of the APRs specifies access protection responsive to each LINK. Each of the programmable instructions corresponds to the APR (source APR) associated with a memory range in which the programmable instruction is stored, and corresponds to the LINK (source LINK) associated with the respective source APR.