公开(公告)号：US20220208601A1

公开(公告)日：2022-06-30

申请号：US17695119

申请日：2022-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20200328275A1

公开(公告)日：2020-10-15

申请号：US16384700

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian LIN ,  Frank Alexander BAIOCCHI ,  Seetharaman SRIDHAR

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

公开(公告)号：US20200243647A1

公开(公告)日：2020-07-30

申请号：US16846754

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong KIM ,  Seetharaman SRIDHAR ,  Sameer PENDHARKAR

IPC: H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

公开(公告)号：US20190206997A1

公开(公告)日：2019-07-04

申请号：US15876989

申请日：2018-01-22

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong KIM ,  Seetharaman SRIDHAR ,  Sameer PENDHARKAR

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0882 ,  H01L29/0623 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

公开(公告)号：US20160225897A1

公开(公告)日：2016-08-04

申请号：US15093277

申请日：2016-04-07

Applicant: Texas Instruments Incorporated

Inventor： Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L21/027 ,  H01L21/762

Abstract: An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.

公开(公告)号：US20150171211A1

公开(公告)日：2015-06-18

申请号：US14563028

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。