公开(公告)号：US20140183662A1

公开(公告)日：2014-07-03

申请号：US14101435

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Eugen MINDRICELU ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L27/02 ,  H01L21/761

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract translation: 在包含具有第一导电类型的半导体材料的基板上形成集成电路。 在第一导电类型的半导体材料中形成具有第二相对导电类型的深阱。 通过深井在衬底中形成深的隔离沟槽，以将深井的未使用部分与深井的功能部分分开。 深井的功能部分包含集成电路的有源电路元件。 深井的分离部分不包含有源电路元件。 在深井的分离部分中形成具有第二导电类型和比深阱更高的平均掺杂密度的接触区域。 接触区域连接到集成电路的电压端子。

公开(公告)号：US20190157142A1

公开(公告)日：2019-05-23

申请号：US16241143

申请日：2019-01-07

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Abbas ALI ,  Yaping CHEN ,  Chao ZUO ,  Seetharaman SRIDHAR ,  Yunlong LIU

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3213

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US20170062611A1

公开(公告)日：2017-03-02

申请号：US15348725

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/266 ,  H01L21/762

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

公开(公告)号：US20230101610A1

公开(公告)日：2023-03-30

申请号：US17490918

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Meng-Chia LEE ,  Sunglyong KIM ,  Seetharaman SRIDHAR ,  Sameer PENDHARKAR

IPC: H01L29/78

Abstract: An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

公开(公告)号：US20150187937A1

公开(公告)日：2015-07-02

申请号：US14557648

申请日：2014-12-02

Applicant: Texas Instruments Incorporated

Inventor： Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/311 ,  H01L29/04 ,  H01L29/16 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7835 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7833

Abstract: An integrated circuit on a rotated substrate with an LDMOS transistor. A method of enhancing the CHC performance of an LDMOS transistor by growing a second STI liner oxide. A method of enhancing the CHC performance of an LDMOS transistor building the LDMOS transistor on a rotated substrate and growing a second STI liner oxide.

Abstract translation: 在具有LDMOS晶体管的旋转衬底上的集成电路。 通过生长第二STI衬垫氧化物来增强LDMOS晶体管的CHC性能的方法。 一种增强LDMOS晶体管的CHC性能的方法，其在旋转的衬底上构建LDMOS晶体管并生长第二STI衬里氧化物。

公开(公告)号：US20150179792A1

公开(公告)日：2015-06-25

申请号：US14572923

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L21/762 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L21/027 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/0271 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.

Abstract translation: 一种具有扩展漏极MOS晶体管的集成电路和方法，其中扩散漏极在漏极中的场氧化物元件下方比在栅极下方的漂移区域更深。 蚀刻场氧化物硬掩模层以限定漏极场氧化物沟槽区域。 通过漏极场氧化物沟槽区域注入漏极掺杂物，并执行热释放驱动。 接着，形成漏极场氧化物元件。

公开(公告)号：US20200312710A1

公开(公告)日：2020-10-01

申请号：US16546499

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20160315159A1

公开(公告)日：2016-10-27

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Yufei XIONG ,  Yunlong LIU ,  Zachary K. LEE ,  Peng HU

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L21/288 ,  H01L29/08 ,  H01L29/732 ,  H01L21/285 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料

公开(公告)号：US20150187957A1

公开(公告)日：2015-07-02

申请号：US14584369

申请日：2014-12-29

Applicant: Texas Instruments Incorporated

Inventor： Hao DING ,  Seetharaman SRIDHAR

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66477 ,  H01L21/823462 ,  H01L27/088

Abstract: An integrated circuit and method with a radiation hard transistor where the gate of the radiation hard transistor does not cross the boundary between active and isolation.

Abstract translation: 一种具有放射硬晶体管的集成电路和方法，其中辐射硬晶体管的栅极不跨越有源和隔离之间的边界。

公开(公告)号：US20220223731A1

公开(公告)日：2022-07-14

申请号：US17147875

申请日：2021-01-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong KIM ,  Seetharaman SRIDHAR ,  Meng-Chia LEE ,  Thomas Eugene GREBS ,  Hong YANG

IPC: H01L29/78 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.