公开(公告)号：US20180261495A1

公开(公告)日：2018-09-13

申请号：US15649774

申请日：2017-07-14

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Michael F. CHISHOLM ,  Yufei XIONG ,  Yunlong LIU

IPC: H01L21/762

Abstract: In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

公开(公告)号：US20180204917A1

公开(公告)日：2018-07-19

申请号：US15601591

申请日：2017-05-22

Applicant: Texas Instruments Incorporated

Inventor： Furen LIN ,  Frank BAIOCCHI ,  Haian LIN ,  Yunlong LIU ,  Lark LIU ,  Wei SONG ,  ZiQiang ZHAO

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/41741 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7834

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

公开(公告)号：US20200312710A1

公开(公告)日：2020-10-01

申请号：US16546499

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20180102424A1

公开(公告)日：2018-04-12

申请号：US15831112

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Yufei XIONG ,  Yunlong LIU ,  Hong YANG ,  Ho LIN ,  Tian Ping LV ,  Sheng ZOU ,  Qiu Ling JIA

IPC: H01L29/739 ,  H01L21/3213 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/743 ,  H01L23/485 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7827

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US20160315159A1

公开(公告)日：2016-10-27

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Yufei XIONG ,  Yunlong LIU ,  Zachary K. LEE ,  Peng HU

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L21/288 ,  H01L29/08 ,  H01L29/732 ,  H01L21/285 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料

公开(公告)号：US20220208601A1

公开(公告)日：2022-06-30

申请号：US17695119

申请日：2022-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20190004201A1

公开(公告)日：2019-01-03

申请号：US16101867

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen LIN ,  Frank BAIOCCHI ,  Haian LIN ,  Yunlong LIU ,  Lark LIU ,  Wei SONG ,  ZiQiang ZHAO

IPC: G01V1/38 ,  G01V1/24 ,  G01V1/16 ,  G01V1/18

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

公开(公告)号：US20160372463A1

公开(公告)日：2016-12-22

申请号：US15255311

申请日：2016-09-02

Applicant: Texas Instruments Incorporated

Inventor： Yufei XIONG ,  Yunlong LIU ,  Hong YANG ,  Jianxin LIU

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract translation: 一种集成电路，其包括在衬底中的沟槽，其具有在沟槽的侧壁和底部上生长的高质量沟槽氧化物，其中形成在侧壁上的高质量沟槽氧化物的厚度与形成在底部上的厚度之比较小 超过1.2。 包括具有高质量氧化物的沟槽的集成电路通过首先在1050℃至1250℃的温度范围内在稀释氧中生长牺牲氧化物而形成，剥离牺牲氧化物，在稀释氧中生长高质量的氧化物 在1050℃至1250℃的温度下加入反式1,2-二氯乙烯，并在1050℃至1250℃的温度范围内在惰性环境中退火高品质氧化物。

公开(公告)号：US20210272842A1

公开(公告)日：2021-09-02

申请号：US17322274

申请日：2021-05-17

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Michael F. CHISHOLM ,  Yufei XIONG ,  Yunlong LIU

IPC: H01L21/762

Abstract: In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

公开(公告)号：US20190157142A1

公开(公告)日：2019-05-23

申请号：US16241143

申请日：2019-01-07

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Abbas ALI ,  Yaping CHEN ,  Chao ZUO ,  Seetharaman SRIDHAR ,  Yunlong LIU

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3213

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.