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公开(公告)号：US11171601B1
公开(公告)日：2021-11-09
申请号：US16942230
申请日：2020-07-29
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Theertham , Srikanth Manian , Uday Kiran Meda
Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.
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公开(公告)号：US09509323B2
公开(公告)日：2016-11-29
申请号：US14709759
申请日：2015-05-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Krishnaswamy Thiagarajan , Jagdish Chand Goyal , Srikanth Manian , Debapriya Sahu
CPC classification number: H03L7/1976 , H03L7/0814 , H03L7/1974 , H03L2207/10 , H04B1/40 , H04L7/033 , H04L7/0331
Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。
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公开(公告)号：US10250248B2
公开(公告)日：2019-04-02
申请号：US16057979
申请日：2018-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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Patent Agency Ranking
公开(公告)号：US20180351541A1
公开(公告)日：2018-12-06
申请号：US16057979
申请日：2018-08-08
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
CPC classification number: H03K5/26 , H03K5/135 , H03K5/1502 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/18
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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公开(公告)号：US10075156B2
公开(公告)日：2018-09-11
申请号：US15673166
申请日：2017-08-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
CPC classification number: H03K5/26 , H03K5/135 , H03K5/1502 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/18
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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公开(公告)号：US09954705B2
公开(公告)日：2018-04-24
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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17.发明授权公开(公告)号：US09667300B2
公开(公告)日：2017-05-30
申请号：US14753940
申请日：2015-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H04B1/40 , H03L7/1075 , H03L7/1976
Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.
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公开(公告)号：US20150091385A1
公开(公告)日：2015-04-02
申请号：US14040275
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Yogesh Darwhekar , Abhishek Agarwal , Koby Levy , Yaniv Tzoreff , Erez Shalom
CPC classification number: H04B5/0037
Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.
Abstract translation: 一种在可以是NFC（近场通信）设备的电子通信设备中对功率采集的电源进行充电的方法。 在电子通信设备中收取的电力被充电而不引起dV / V违规，并避免虚假唤醒。 在电子通信设备的天线处接收RF（射频）字段。 在电子通信设备的第一标签引脚和第二标签引脚处的RF场产生差分电压。 响应于差分电压产生带隙参考电压和参考电流。 响应于差分电压和带隙基准电压产生并联电流。 如果分流电流大于参考电流，则一组开关器件被激活。
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