公开(公告)号：US20230161675A1

公开(公告)日：2023-05-25

申请号：US18151543

申请日：2023-01-09

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F11/14

CPC classification number: G06F11/1497 ,  G06F2201/87

Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

公开(公告)号：US20230041617A1

公开(公告)日：2023-02-09

申请号：US17564975

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/42 ,  G06F13/40 ,  G06F12/1027

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US20220206970A1

公开(公告)日：2022-06-30

申请号：US17697114

申请日：2022-03-17

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY

IPC: G06F13/20 ,  G06F13/42

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

公开(公告)号：US20240354272A1

公开(公告)日：2024-10-24

申请号：US18763195

申请日：2024-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F21/45

CPC classification number: G06F13/4027 ,  G06F13/1668 ,  G06F13/4282 ,  G06F21/45 ,  G06F2213/0026

Abstract: Examples systems are provided for isolating transactions originating from different types of applications, including systems for providing such isolation on an inbound side and systems for providing such isolation on an outbound side, as well as end-to-end isolation systems. Such systems may be implemented in a peripheral component interconnect express (PCIe) environment. On an outbound side, a first interconnect receives transactions having different attributes indicating different application origins, respectively, and selects different pathways for the transactions based on their respective attributes. On an inbound side, a second interconnect selects different pathways for the transactions based on their respective attributes. Thus, transactions originating from safety and non-safety applications may be kept isolated as they are routed, and a non-safety transaction may be restricted from accessing certain portions of memory.

公开(公告)号：US20240022528A1

公开(公告)日：2024-01-18

申请号：US18357710

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: H04L49/90 ,  H04L49/109 ,  H04L69/22 ,  H04L67/568

CPC classification number: H04L49/9042 ,  H04L49/109 ,  H04L69/22 ,  H04L67/568

Abstract: In an example, a system includes a network port that receives a packet; a first memory; a second memory; and a packet analyzer coupled to the network port. The packet analyzer operates to divide the packet into multiple fragments, analyze each of the multiple fragments to determine whether the corresponding fragment has a first priority level or a second, lower, priority level, determine whether to store each of the multiple fragments in the first memory or the second memory based on the priority level determined for that fragment, store each fragment determined to have the first priority level in the first memory, and store each fragment determined to have the second priority level in the second memory. The network port, packet analyzer and the first memory, which may be a cache memory, may be embodied on a chip, and the second memory may be external to the chip.

公开(公告)号：US20230222072A1

公开(公告)日：2023-07-13

申请号：US18186524

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY ,  Jason A.T. Jones

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

公开(公告)号：US20220391219A1

公开(公告)日：2022-12-08

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Denis Roland BEAUDOIN ,  Gregory Raymond SHURTZ ,  Santhanakrishnan Badri NARAYANAN ,  Mark Adrian BRYANS ,  Mihir Narendra MODY ,  Jason A.T. JONES ,  Jayant THAKUR

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20210232515A1

公开(公告)日：2021-07-29

申请号：US17134861

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY

IPC: G06F13/20 ,  G06F13/42

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

公开(公告)号：US20210203622A1

公开(公告)日：2021-07-01

申请号：US17122215

申请日：2020-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: H04L12/861 ,  H04L29/06 ,  H04L29/08 ,  H04L12/933

Abstract: In some examples, a system on chip (SOC) comprises a network switch configured to receive a packet and to identify a flow identifier (ID) corresponding to a header of the packet. The SOC comprises a direct memory access (DMA) controller coupled to the network switch, where the DMA controller is configured to divide the packet into first and second fragments based on the flow ID and to assign a first hardware queue to the first fragment and a second hardware queue to the second fragment, and wherein the DMA controller is further configured to assign memory regions to the first and second fragments based on the first and second hardware queues. The SOC comprises a snoopy cache configured to store the first fragment to the snoopy cache or to memory based on a first cache allocation command, where the first cache allocation command is based on the memory region assigned to the first fragment, where the snoopy cache is further configured to store the second fragment to the snoopy cache or to memory based on a second cache allocation command, and where the second cache allocation command is based on the memory region assigned to the second fragment.

公开(公告)号：US20210200707A1

公开(公告)日：2021-07-01

申请号：US17135129

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F21/45

Abstract: In some examples, a method includes receiving a transaction at an inbound port, the transaction including a requester identification (ID), a traffic class, and a peripheral component interconnect express (PCIe) address. The method includes providing an attribute based at least in part on the traffic class. The method includes providing a context ID based on the attribute and the requester ID. The method includes accessing a region of memory responsive to the transaction, the region of memory corresponding to the context ID.