公开(公告)号：US09741624B2

公开(公告)日：2017-08-22

申请号：US15193270

申请日：2016-06-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/31 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

公开(公告)号：US20170221895A1

公开(公告)日：2017-08-03

申请号：US15490466

申请日：2017-04-18

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/518

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

公开(公告)号：US09093303B2

公开(公告)日：2015-07-28

申请号：US13906500

申请日：2013-05-31

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract translation: 可以通过从MOS晶体管栅极的侧壁上的偏移间隔物去除源/漏间隔物来形成集成电路，在MOS晶体管栅极的侧表面上形成接触蚀刻停止层（CESL）间隔层，蚀刻CESL间隔层以形成 在MOS晶体管栅极的横向表面上倾斜的CESL间隔物，其高度为MOS晶体管栅极的1/4至¾，在倾斜的CESL间隔物，MOS晶体管栅极和介入衬底上形成CESL，并在CESL上形成PMD层 。

公开(公告)号：US20140021556A1

公开(公告)日：2014-01-23

申请号：US13906500

申请日：2013-05-31

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract translation: 可以通过从MOS晶体管栅极的侧壁上的偏移间隔物去除源/漏间隔物来形成集成电路，在MOS晶体管栅极的侧表面上形成接触蚀刻停止层（CESL）间隔层，蚀刻CESL间隔层以形成 在MOS晶体管栅极的横向表面上倾斜的CESL间隔物，其高度为MOS晶体管栅极的1/4至¾，在倾斜的CESL间隔物，MOS晶体管栅极和介入衬底上形成CESL，并在CESL上形成PMD层 。

公开(公告)号：US09659935B2

公开(公告)日：2017-05-23

申请号：US14745793

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/285 ,  H01L21/768 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/518

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

公开(公告)号：US09437449B2

公开(公告)日：2016-09-06

申请号：US14142075

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中去除氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US09224657B2

公开(公告)日：2015-12-29

申请号：US13960517

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。

公开(公告)号：US20150287723A1

公开(公告)日：2015-10-08

申请号：US14745793

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L27/092 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/518

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract translation: 一种用于形成MOS晶体管的方法，包括提供包括在其上的栅极电介质上具有栅电极的半导体表面的衬底，栅电极的侧壁上的电介质间隔物，栅电极的相对侧上的半导体表面中的源极和漏极，以及 在栅极电极上方和源极和漏极区域上的金属前电介质（PMD）层。 通过PMD层形成接触孔，以形成与栅电极的接触并与源极和漏极接触。 然后将接触后蚀刻介电层沉积到PMD层的源极和漏极以及侧壁上。 从触点选择性地去除接触后蚀刻介电层，以在PMD层的侧壁上留下介电衬垫。 在源极和漏极的触点上形成金属硅化物层。

公开(公告)号：US09093380B2

公开(公告)日：2015-07-28

申请号：US13910801

申请日：2013-06-05

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L21/285 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/518

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PAD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract translation: 一种用于形成MOS晶体管的方法，包括提供一种衬底，该衬底包括在其上的栅极电介质上具有栅电极的半导体表面，在栅电极的侧壁上的电介质间隔物，栅电极的相对侧上的半导体表面中的源极和漏极，以及 栅极电极上方和源极和漏极区域上的预金属电介质（PAD）层。 通过PMD层形成接触孔，以形成与栅电极的接触并与源极和漏极接触。 然后将接触后蚀刻介电层沉积到PMD层的源极和漏极以及侧壁上。 从触点选择性地去除接触后蚀刻介电层，以在PMD层的侧壁上留下介电衬垫。 在源极和漏极的触点上形成金属硅化物层。

公开(公告)号：US20150044830A1

公开(公告)日：2015-02-12

申请号：US13960517

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Brian K. Kirkpatrick

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract translation: 集成电路形成为包括第一极性MOS晶体管和第二相反极性MOS晶体管。 在第一极性MOS晶体管和第二极性MOS晶体管上形成具有1原子％至30原子％硅的硅掺杂氮化硼（SixBN）的硬掩模。 硬掩模从第一极性MOS晶体管的源极/漏极区域移除，并且在第二极性MOS晶体管上保持原位。 半导体材料在第一极性MOS晶体管的源极/漏极区域外延生长，同时硬掩模就位。 随后，从第二极性MOS晶体管去除硬掩模。