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公开(公告)号：US09762292B2
公开(公告)日：2017-09-12
申请号：US14040275
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Yogesh Darwhekar , Abhishek Agrawal , Koby Levy , Yaniv Tzoreff , Erez Shalom
IPC: H04B5/00
CPC classification number: H04B5/0037
Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.
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公开(公告)号：US20240113722A1
公开(公告)日：2024-04-04
申请号：US18534861
申请日：2023-12-11
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan , Yogesh Darwhekar , Subhashish Mukherjee
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
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公开(公告)号：US11626840B2
公开(公告)日：2023-04-11
申请号：US17462941
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arpan Sureshbhai Thakkar , Pranav Kumar , Yogesh Darwhekar
IPC: H03D7/14 , H03K5/1252
Abstract: A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.
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公开(公告)号：US20230013907A1
公开(公告)日：2023-01-19
申请号：US17377698
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Jayawardan Janardhanan , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
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公开(公告)号：US11500336B1
公开(公告)日：2022-11-15
申请号：US17317628
申请日：2021-05-11
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Subhashish Mukherjee , Narala Raghavendra Reddy
Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.
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Patent Agency Ranking
公开(公告)号：US09954705B2
公开(公告)日：2018-04-24
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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公开(公告)号：US09661450B2
公开(公告)日：2017-05-23
申请号：US15041966
申请日：2016-02-11
Applicant: Texas Instruments Incorporated
Inventor： Abhishek Agrawal , Yogesh Darwhekar
CPC classification number: H04W4/80 , G06K7/10237 , H04B5/0056
Abstract: An electronic communication device includes an antenna configured to receive a radio frequency (RF) signal and generate a differential current signal. A mixer circuit is configured to downconvert a differential voltage to generate an output voltage. The differential voltage is generated from the differential current signal, and the output voltage is used for detecting the RF signal.
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公开(公告)号：US09594388B2
公开(公告)日：2017-03-14
申请号：US14973159
申请日：2015-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Agrawal , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: G05F1/613 , H02M7/217 , H04B5/0031
Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
Abstract translation: 数字分流调节器在天线处接收射频（RF）信号，其在差分路径上产生差分输出信号。 峰值检测器耦合到天线，并通过差分路径接收差分输出信号。 第一比较器接收峰值检测器的电压输出和第一电压。 第二比较器接收峰值检测器的电压输出和第二电压。 数字状态机接收第一比较器的输出和第二比较器的输出。 多个并联NMOS晶体管接收数字状态机的输出。 数字状态机被配置为控制被激活的并联NMOS晶体管的数量，以将峰值检测器的电压输出保持在第一电压和第二电压之间。
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19.发明申请SHARED ANTENNA SOLUTION FOR WIRELESS CHARGING AND NEAR FIELD COMMUNICATION 审中-公开用于无线充电和近场通信的共享天线解决方案公开(公告)号：US20150091502A1
公开(公告)日：2015-04-02
申请号：US14043516
申请日：2013-10-01
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: H02J50/10 , H01Q1/38 , H01Q7/00 , H01Q21/28 , H02J7/025 , H02J17/00 , H04B5/0031 , H04B5/0037 , H04B5/0081 , Y10T29/49018
Abstract: A method of coupling a first port of a single antenna to a first coupling circuit and a second port of the single antenna to a second coupling circuit. The method includes coupling a wireless charging unit to the first coupling unit and coupling an NFC transceiver block to the second coupling circuit. The method further includes isolating the single antenna from the wireless charging unit during a time interval when the NFC transceiver block is operational and isolating the single antenna from the NFC transceiver block during a time interval when the wireless charging unit is operational.
Abstract translation: 一种将单个天线的第一端口耦合到单个天线的第一耦合电路和第二端口到第二耦合电路的方法。 该方法包括将无线充电单元耦合到第一耦合单元并将NFC收发器模块耦合到第二耦合电路。 该方法还包括在NFC收发器模块运行的时间间隔期间隔离单个天线与无线充电单元的隔离，并且在无线充电单元可操作的时间间隔期间将单个天线与NFC收发器模块隔离开。
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公开(公告)号：US20150091385A1
公开(公告)日：2015-04-02
申请号：US14040275
申请日：2013-09-27
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Yogesh Darwhekar , Abhishek Agarwal , Koby Levy , Yaniv Tzoreff , Erez Shalom
CPC classification number: H04B5/0037
Abstract: A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current.
Abstract translation: 一种在可以是NFC（近场通信）设备的电子通信设备中对功率采集的电源进行充电的方法。 在电子通信设备中收取的电力被充电而不引起dV / V违规，并避免虚假唤醒。 在电子通信设备的天线处接收RF（射频）字段。 在电子通信设备的第一标签引脚和第二标签引脚处的RF场产生差分电压。 响应于差分电压产生带隙参考电压和参考电流。 响应于差分电压和带隙基准电压产生并联电流。 如果分流电流大于参考电流，则一组开关器件被激活。
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