公开(公告)号：US20210202524A1

公开(公告)日：2021-07-01

申请号：US17201252

申请日：2021-03-15

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.

公开(公告)号：US20210090616A1

公开(公告)日：2021-03-25

申请号：US17109853

申请日：2020-12-02

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20200090710A1

公开(公告)日：2020-03-19

申请号：US16356980

申请日：2019-03-18

Applicant: Toshiba Memory Corporation

Inventor： Keisuke NAKATSUKA ,  Tomoya SANUKI ,  Takashi MAEDA ,  Go SHIKATA ,  Hideaki AOCHI

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/18 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11573

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20190333928A1

公开(公告)日：2019-10-31

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Keisuke NAKATSUKA ,  Fumitaka ARAI ,  Shinya ARAI ,  Yasuhiro UCHIYAMA

IPC: H01L27/11578 ,  H01L27/1157 ,  G11C11/40

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US20190259775A1

公开(公告)日：2019-08-22

申请号：US16126209

申请日：2018-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/40

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrode films, a semiconductor member, a tunneling insulating film, a charge storage member, and a blocking insulating film. The plurality of electrode films are arranged to be separated from each other along a first direction. The semiconductor member extends in the first direction. The tunneling insulating film is provided between the semiconductor member and the electrode films. The charge storage member is provided between the tunneling insulating film and the electrode films. The blocking insulating film is provided between the charge storage member and the electrode films. The blocking insulating film includes a first film contacting the charge storage film and including carbon-containing silicon oxide, and a second film contacting the electrode films and including hafnium oxide or aluminum oxide.