公开(公告)号：US20210175367A1

公开(公告)日：2021-06-10

申请号：US17181315

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10930498B2

公开(公告)日：2021-02-23

申请号：US16598275

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/8234

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US10714592B2

公开(公告)日：2020-07-14

申请号：US15798270

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chen-Feng Hsu ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US10361278B2

公开(公告)日：2019-07-23

申请号：US15725655

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Tung Ying Lee ,  Shao-Ming Yu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chao-Hsien Huang

IPC: H01L29/49 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20190103472A1

公开(公告)日：2019-04-04

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/51 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US10062782B2

公开(公告)日：2018-08-28

申请号：US15429861

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chih Chieh Yeh ,  Cheng-Hsien Wu ,  Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Tsung-Lin Lee ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7853

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US10038080B1

公开(公告)日：2018-07-31

申请号：US15498727

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/306

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with the first dummy gate; forming a spacer layer in contact with the first dummy gate and the epitaxy structure; and replacing the first dummy gate with a metal gate stack.

公开(公告)号：US20250151337A1

公开(公告)日：2025-05-08

申请号：US19014431

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H10D30/67 ,  H10D30/01 ,  H10D62/10 ,  H10D64/01 ,  H10D84/85

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US12211895B2

公开(公告)日：2025-01-28

申请号：US17202237

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

公开(公告)号：US20240379832A1

公开(公告)日：2024-11-14

申请号：US18783516

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Tzu Ang Chao ,  Chao-Ching Cheng ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/8256 ,  H01L23/31 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K10/84 ,  H10K10/88 ,  H10K19/10 ,  H10K85/20

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.