公开(公告)号：US09134604B2

公开(公告)日：2015-09-15

申请号：US14015885

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD

Inventor： Chih-Tsung Shih ,  Hsin-Chieh Yao ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Chung-Ju Lee ,  Anthony Yen

IPC: G03F1/24 ,  G03F1/52 ,  G03F1/54 ,  G03F1/58

CPC classification number: G03F1/58 ,  G03F1/24 ,  G03F1/52 ,  G03F1/54

Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.

Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。

公开(公告)号：US20150064611A1

公开(公告)日：2015-03-05

申请号：US14015885

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chih-Tsung Shih ,  Hsin-Chieh Yao ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Chung-Ju Lee ,  Anthony Yen

IPC: G03F1/58 ,  G03F1/52

CPC classification number: G03F1/58 ,  G03F1/24 ,  G03F1/52 ,  G03F1/54

Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.

Abstract translation: 提供含Cu材料作为EUV掩模的吸收层。 利用含Cu材料的吸收层，根据本公开的各种实施方案，仅通过吸收层的厚度仅为30nm可以实现70nm厚度的TaBN中的常规吸收体的相同的光刻性能。 此外，可以减少193-257nm的辐射光的带外（OOB）光斑，以获得更好的光刻性能。

公开(公告)号：US11521896B2

公开(公告)日：2022-12-06

申请号：US17012427

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L27/092

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.

公开(公告)号：US20210391296A1

公开(公告)日：2021-12-16

申请号：US16898670

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/00 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US20210375751A1

公开(公告)日：2021-12-02

申请号：US16887475

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.