公开(公告)号：US11056401B2

公开(公告)日：2021-07-06

申请号：US16700227

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.

公开(公告)号：US10811318B2

公开(公告)日：2020-10-20

申请号：US16730320

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/8234 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

公开(公告)号：US10804375B2

公开(公告)日：2020-10-13

申请号：US15631012

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng Yun ,  Shao-Ming Yu ,  Tung-Ying Lee ,  Chih-Chieh Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.

公开(公告)号：US09876117B2

公开(公告)日：2018-01-23

申请号：US15478758

申请日：2017-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih-Chieh Yeh ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/70 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/78 ,  H01L23/31 ,  H01L21/324 ,  H01L21/322 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature. The passivation layer separates the fin structure from the interfacial layer.

公开(公告)号：US09660025B2

公开(公告)日：2017-05-23

申请号：US14840904

申请日：2015-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih-Chieh Yeh ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L21/70 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/06 ,  H01L29/66 ,  H01L21/322

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

公开(公告)号：US11348920B2

公开(公告)日：2022-05-31

申请号：US17066424

申请日：2020-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.

公开(公告)号：US10665569B2

公开(公告)日：2020-05-26

申请号：US15795191

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng Yun ,  Shao-Ming Yu ,  Chih-Chieh Yeh

IPC: H01L25/04 ,  H01L21/70 ,  H01L21/027 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.

公开(公告)号：US10522409B2

公开(公告)日：2019-12-31

申请号：US15692768

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/8234 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure also includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

公开(公告)号：US10181524B1

公开(公告)日：2019-01-15

申请号：US15649724

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng Yun ,  Shao-Ming Yu ,  Chih-Chieh Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/105 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.

公开(公告)号：US10038080B1

公开(公告)日：2018-07-31

申请号：US15498727

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/306

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with the first dummy gate; forming a spacer layer in contact with the first dummy gate and the epitaxy structure; and replacing the first dummy gate with a metal gate stack.