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    Memory Array Including Epitaxial Source Lines and Bit Lines
    13.
    发明申请
    Memory Array Including Epitaxial Source Lines and Bit Lines 有权

    公开(公告)号：US20220384484A1

    公开(公告)日：2022-12-01

    申请号：US17884348

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H01L27/11597 ,  H01L29/06 ,  H01L27/11587

    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

    FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME
    15.
    发明申请
    FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210375933A1

    公开(公告)日：2021-12-02

    申请号：US17117570

    申请日：2020-12-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L21/02

    Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

    Memory Array Contact Structures
    19.
    发明申请
    Memory Array Contact Structures 有权

    公开(公告)号：US20220384348A1

    公开(公告)日：2022-12-01

    申请号：US17818638

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

    IPC: H01L23/535 ,  H01L27/1159 ,  H01L27/11597

    Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD
    20.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD 有权

    公开(公告)号：US20220285393A1

    公开(公告)日：2022-09-08

    申请号：US17193331

    申请日：2021-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

    IPC: H01L27/11597 ,  H01L21/02 ,  H01L23/522 ,  H01L27/1159 ,  H01L29/24

    Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

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