公开(公告)号：US11810827B2

公开(公告)日：2023-11-07

申请号：US17338929

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7846 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823892 ,  H01L27/0928

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US11031299B2

公开(公告)日：2021-06-08

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US10466731B2

公开(公告)日：2019-11-05

申请号：US15007684

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  H01L27/088 ,  H01L29/78 ,  G05F3/24 ,  H01L21/8234 ,  H01L29/06

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

公开(公告)号：US20180356852A1

公开(公告)日：2018-12-13

申请号：US16106476

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L29/78 ,  H01L29/06 ,  G05F1/595 ,  G05F1/46 ,  H01L21/8234 ,  H01L27/088

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

公开(公告)号：US20170212545A1

公开(公告)日：2017-07-27

申请号：US15007684

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: G05F3/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: G05F3/16 ,  G05F1/465 ,  G05F1/468 ,  G05F1/595 ,  G05F3/247 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/785

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

公开(公告)号：US11276766B2

公开(公告)日：2022-03-15

申请号：US16673661

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US10534393B2

公开(公告)日：2020-01-14

申请号：US16106476

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  G05F3/24

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

公开(公告)号：US09537010B2

公开(公告)日：2017-01-03

申请号：US14613663

申请日：2015-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chien-Tai Chan ,  Da-Wen Lin ,  Huicheng Chang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括在衬底的上部具有掺杂区的衬底。 掺杂区域掺杂有第一导电类型的第一掺杂剂。 半导体器件结构包括在衬底上的一个鳍结构。 通过鳍结构暴露的掺杂区域的第一掺杂剂浓度大于由鳍结构覆盖的掺杂区域的第二掺杂剂浓度。 半导体器件结构包括在衬底上并在鳍结构的两个相对侧的隔离层。 半导体器件结构包括隔离层上的栅极和鳍结构。

公开(公告)号：US20210366784A1

公开(公告)日：2021-11-25

申请号：US17338929

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US11150680B2

公开(公告)日：2021-10-19

申请号：US16578361

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yvonne Lin ,  Da-Wen Lin ,  Peter Huang ,  Paul Rousseau ,  Sheng-Jier Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  G05F3/16 ,  G05F1/46 ,  G05F1/595 ,  G05F3/24

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.