公开(公告)号：US20170365707A1

公开(公告)日：2017-12-21

申请号：US15693171

申请日：2017-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

公开(公告)号：US20210280579A1

公开(公告)日：2021-09-09

申请号：US17327123

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Wei-Yuan LU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/22

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US20210273079A1

公开(公告)日：2021-09-02

申请号：US16949446

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

公开(公告)号：US20210118749A1

公开(公告)日：2021-04-22

申请号：US17113209

申请日：2020-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define an air gap therebetween. The second spacer seals the air gap between the first spacer and the epitaxy structure. The dielectric residue is in the air gap and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue.

公开(公告)号：US20200027793A1

公开(公告)日：2020-01-23

申请号：US16585859

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20180102292A1

公开(公告)日：2018-04-12

申请号：US15830859

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20170243957A1

公开(公告)日：2017-08-24

申请号：US15590301

申请日：2017-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung LO ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI ,  Ying-Ho CHEN

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

公开(公告)号：US20160181414A1

公开(公告)日：2016-06-23

申请号：US14579708

申请日：2014-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract translation: 半导体器件包括用于第一鳍式场效应晶体管（FET）的第一鳍结构。 第一鳍结构包括从基板突出的第一基底层，设置在第一基底层上的第一中间层和设置在第一中间层上的第一沟道层。 第一翅片结构还包括由防止下层氧化的材料制成的第一保护层。 第一沟道层由SiGe制成，第一中间层包括设置在第一基极层上的第一半导体（例如，SiGe）层和设置在第一半导体层上的第二半导体层（例如Si）。 第一保护层覆盖第一基底层的侧壁，第一半导体层的侧壁和第二半导体层的侧壁。

公开(公告)号：US20230253478A1

公开(公告)日：2023-08-10

申请号：US18297824

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsieh WONG ,  Wei-Yang LEE ,  Yen-Ming CHEN ,  Feng-Cheng YANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/0649 ,  H01L21/02293 ,  H01L29/511 ,  H01L29/66636 ,  H01L21/022 ,  H01L29/66553

Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

公开(公告)号：US20210273101A1

公开(公告)日：2021-09-02

申请号：US17320687

申请日：2021-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.