公开(公告)号：US12087801B2

公开(公告)日：2024-09-10

申请号：US17646765

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Chih-Yu Lai ,  Shih Pei Chou ,  Yen-Ting Chiang ,  Hsiao-Hui Tseng ,  Min-Ying Tsai

IPC: H01L27/146 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/14687 ,  H01L21/76229 ,  H01L27/1463 ,  H01L29/0653

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

公开(公告)号：US20210210534A1

公开(公告)日：2021-07-08

申请号：US16736134

申请日：2020-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Chia Ching Liao ,  Yen-Yu Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

公开(公告)号：US10510789B2

公开(公告)日：2019-12-17

申请号：US16352108

申请日：2019-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L21/00 ,  H01L27/146

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.

公开(公告)号：US10475828B2

公开(公告)日：2019-11-12

申请号：US15868324

申请日：2018-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Chun-Yuan Chen ,  Hsiao-Hui Tseng ,  Yu-Jen Wang ,  Shyh-Fann Ting ,  Wei-Chuang Wu ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/11

Abstract: An image sensor device structure is provided. The image sensor device structure includes a substrate, and the substrate is doped with a first conductivity type. The image sensor device structure includes a light-sensing region formed in the substrate, and the light-sensing region is doped with a second conductivity type that is different from the first conductivity type. The image sensor device structure further includes a doping region extended into the light-sensing region, and the doping region is doped with the first conductivity type. The image sensor device structure also includes a plurality of color filters formed on the doping region.

公开(公告)号：US10304886B2

公开(公告)日：2019-05-28

申请号：US15795681

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Yu-Jen Wang ,  Chun-Yuan Chen

IPC: H01L27/146

Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.

公开(公告)号：US20180204862A1

公开(公告)日：2018-07-19

申请号：US15919784

申请日：2018-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

公开(公告)号：US20240363671A1

公开(公告)日：2024-10-31

申请号：US18768642

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Chih-Yu Lai ,  Shih Pei Chou ,  Yen-Ting Chiang ,  Hsiao-Hui Tseng ,  Min-Ying Tsai

IPC: H01L27/146 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/14687 ,  H01L21/76229 ,  H01L27/1463 ,  H01L29/0653

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

公开(公告)号：US20220246469A1

公开(公告)日：2022-08-04

申请号：US17352812

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Han Tseng ,  Chun-Yuan Chen ,  Lu-Sheng Chou ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze

IPC: H01L21/768 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US20190214414A1

公开(公告)日：2019-07-11

申请号：US16352108

申请日：2019-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.

公开(公告)号：US20190096929A1

公开(公告)日：2019-03-28

申请号：US15795681

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Yu-Jen Wang ,  Chun-Yuan Chen

IPC: H01L27/146

Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.