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    DIELECTRIC STRUCTURE OVERLYING IMAGE SENSOR ELEMENT TO INCREASE QUANTUM EFFICIENCY
    3.
    发明申请
    DIELECTRIC STRUCTURE OVERLYING IMAGE SENSOR ELEMENT TO INCREASE QUANTUM EFFICIENCY 有权

    公开(公告)号：US20220293647A1

    公开(公告)日：2022-09-15

    申请号：US17197291

    申请日：2021-03-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Ming-Che Lee

    IPC: H01L27/146

    Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.

    IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTURE
    4.
    发明申请
    IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTURE 有权

    公开(公告)号：US20220293457A1

    公开(公告)日：2022-09-15

    申请号：US17197330

    申请日：2021-03-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Tzu-Jui Wang ,  Sheng-Chan Li

    IPC: H01L21/762 ,  H01L27/146

    Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

    Trim wall protection method for multi-wafer stacking
    6.
    发明授权
    Trim wall protection method for multi-wafer stacking 有权

    公开(公告)号：US11152276B2

    公开(公告)日：2021-10-19

    申请号：US16785866

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu

    IPC: H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

    TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING
    8.
    发明申请
    TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING 有权

    公开(公告)号：US20210134694A1

    公开(公告)日：2021-05-06

    申请号：US16785866

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu

    IPC: H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

    DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE
    9.
    发明申请
    DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE 审中-公开

    公开(公告)号：US20190259804A1

    公开(公告)日：2019-08-22

    申请号：US16405102

    申请日：2019-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

    IPC: H01L27/146 ,  H01L21/8238 ,  H01L33/20

    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

    Deep trench isolation shrinkage method for enhanced device performance
    10.
    发明授权
    Deep trench isolation shrinkage method for enhanced device performance 有权

    公开(公告)号：US10325956B2

    公开(公告)日：2019-06-18

    申请号：US15591722

    申请日：2017-05-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

    IPC: H01L33/20 ,  H01L27/146 ,  H01L21/8238

    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

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