DEFECT OFFSET CORRECTION
    11.
    发明申请

    公开(公告)号:US20210065347A1

    公开(公告)日:2021-03-04

    申请号:US17098895

    申请日:2020-11-16

    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.

    INTEGRATED SEMICONDUCTOR DIE PARCELING PLATFORMS

    公开(公告)号:US20220185512A1

    公开(公告)日:2022-06-16

    申请号:US17686299

    申请日:2022-03-03

    Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.

    WAFER CHUCK
    19.
    发明申请

    公开(公告)号:US20160020128A1

    公开(公告)日:2016-01-21

    申请号:US14332643

    申请日:2014-07-16

    CPC classification number: H01L21/6833

    Abstract: A wafer chuck is provided. The wafer chuck includes a main body and a dielectric layer disposed over the main body. The wafer chuck also includes an electrode embedded in the dielectric layer and configured to generate an electrostatic field for retaining a wafer. The wafer chuck further includes a thermal conductive layer embedded in the main body or the dielectric layer. The thermal conductive layer has a lateral thermal conductivity greater than a vertical thermal conductivity.

    Abstract translation: 提供晶片卡盘。 晶片卡盘包括设置在主体上的主体和电介质层。 晶片卡盘还包括嵌入电介质层中并被配置为产生用于保持晶片的静电场的电极。 晶片卡盘还包括嵌入在主体或电介质层中的导热层。 导热层的横向热导率大于垂直热导率。

    NOZZLE GASKET AND NOZZLE STRUCTURE FOR PURGE LOAD PORT

    公开(公告)号:US20250114803A1

    公开(公告)日:2025-04-10

    申请号:US18484339

    申请日:2023-10-10

    Abstract: A plurality of purge nozzles of a purge load port include a nozzle gasket and a nozzle structure to inject a purging fluid into and through an internal chamber of a container (e.g., a FOUP) that is configured to, in operation, transport wafers or workpieces between various locations within a FAB. The nozzle gasket includes a deformable structure that abuts against a surface of a nozzle structure and a sealing structure opposite to the deformable structure that forms a seal between the container and the nozzle gasket. A nozzle hole of a nozzle of the nozzle structure includes a threaded region or portion that is configured to receive a threaded stopper structure to seal off the nozzle hole.

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