公开(公告)号：US10971402B2

公开(公告)日：2021-04-06

申请号：US16443016

申请日：2019-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02

Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.

公开(公告)号：US11710779B2

公开(公告)日：2023-07-25

申请号：US17301482

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/785

Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

公开(公告)号：US11705507B2

公开(公告)日：2023-07-18

申请号：US17333908

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/0262 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

公开(公告)号：US20230058221A1

公开(公告)日：2023-02-23

申请号：US17406874

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/477

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

公开(公告)号：US11038029B2

公开(公告)日：2021-06-15

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

公开(公告)号：US12057495B2

公开(公告)日：2024-08-06

申请号：US18326682

申请日：2023-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

公开(公告)号：US10707333B2

公开(公告)日：2020-07-07

申请号：US16191244

申请日：2018-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.