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公开(公告)号：US20150097264A1
公开(公告)日：2015-04-09
申请号：US14049239
申请日：2013-10-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Che TSAI , Jam-Wem LEE
IPC: H01L27/02 , H01L21/822 , H01L27/08 , H02H9/04 , H01L29/66
CPC classification number: H01L27/0281 , H01L21/822 , H01L27/0255 , H01L27/0688 , H01L27/0814 , H01L29/0649 , H01L29/083 , H01L29/6609 , H01L29/66136 , H01L29/8613 , H01L29/87 , H02H9/046
Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.
Abstract translation: 具有用于CMOS IC器件的ESD保护的多个二极管的二极管串包括二极管串中的第一二极管和最后一个二极管，其中第一二极管和最后一个二极管都形成在硅衬底的底层上，以及 二极管串中的剩余二极管。 剩余的二极管形成在位于底层顶部的顶层上。 二极管串还包括多个导线，其将底层上的第一二极管和最后一个二极管依次连接到顶层上的剩余二极管，以形成二极管串的三维（3D）结构。
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12.发明申请公开(公告)号：US20250089379A1
公开(公告)日：2025-03-13
申请号：US18961118
申请日：2024-11-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tao-Yi HUNG , Wun-Jie LIN , Jam-Wem LEE , Kuo-Ji CHEN
Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
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公开(公告)号：US20220208752A1
公开(公告)日：2022-06-30
申请号：US17699471
申请日：2022-03-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Lin PENG , Li-Wei CHU , Ming-Fu TSAI , Jam-Wem LEE , Yu-Ti SU
Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
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公开(公告)号：US20220139903A1
公开(公告)日：2022-05-05
申请号：US17086076
申请日：2020-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tao-Yi HUNG , Wun-Jie LIN , Jam-Wem LEE , Kuo-Ji CHEN , Chia-En HUANG
IPC: H01L27/02 , H01L27/092 , H01L21/8238
Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.
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公开(公告)号：US20140035039A1
公开(公告)日：2014-02-06
申请号：US14056034
申请日：2013-10-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Che TSAI , Jam-Wem LEE , Yi-Feng CHANG
IPC: H01L27/02
CPC classification number: H01L27/0259 , H01L21/761 , H01L27/0277 , H01L27/0629
Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.
Abstract translation: 静电放电（ESD）保护电路结构包括几个扩散区和MOS晶体管。 电路结构包括形成在第一类型的第一阱中的第一类型的第一扩散区（例如，P型或N型），形成在第一类型的第一阱中的第一类型的第二扩散区 以及形成在第二类型的第一阱中的第二类型的第一扩散区域（例如，N型或P型）。 第一类型的第一井的第一井形成在第一类的第一井中。 MOS晶体管是第二类型，并且包括由与第一类型的第一阱接合的第二类型的第二阱中形成的第二类型的第二扩散区形成的漏极。
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Patent Agency Ranking
16.发明公开公开(公告)号：US20240153950A1
公开(公告)日：2024-05-09
申请号：US18413869
申请日：2024-01-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Feng CHANG , Po-Lin PENG , Jam-Wem LEE
IPC: H01L27/092 , H01L21/8238 , H01L27/02 , H01L29/06 , H01L29/10 , H01L29/87
CPC classification number: H01L27/0921 , H01L21/823871 , H01L27/0262 , H01L29/0649 , H01L29/1083 , H01L29/87
Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
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17.发明公开公开(公告)号：US20240088137A1
公开(公告)日：2024-03-14
申请号：US18513544
申请日：2023-11-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tao-Yi HUNG , Wun-Jie LIN , Jam-Wem LEE , Kuo-Ji CHEN
CPC classification number: H01L27/0288 , H01L27/0255 , H01L27/0266 , H02H9/046
Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
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公开(公告)号：US20230299576A1
公开(公告)日：2023-09-21
申请号：US18323368
申请日：2023-05-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Lin PENG , Yu-Ti SU , Chia-Wei HSU , Ming-Fu TSAI , Shu-Yu SU , Li-Wei CHU , Jam-Wem LEE , Chia-Jung CHANG , Hsiang-Hui CHENG
CPC classification number: H02H9/046 , G01R31/001 , H02H1/0007
Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
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公开(公告)号：US20220294212A1
公开(公告)日：2022-09-15
申请号：US17827776
申请日：2022-05-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Lin PENG , Yu-Ti SU , Chia-Wei HSU , Ming-Fu TSAI , Shu-Yu SU , Li-Wei CHU , Jam-Wem LEE , Chia-Jung CHANG , Hsiang-Hui CHENG
Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
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20.发明申请公开(公告)号：US20220130824A1
公开(公告)日：2022-04-28
申请号：US17570872
申请日：2022-01-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Feng CHANG , Po-Lin PENG , Jam-Wem LEE
IPC: H01L27/092 , H01L29/10 , H01L27/02 , H01L21/8238 , H01L29/06 , H01L29/87
Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
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