公开(公告)号：US11233117B2

公开(公告)日：2022-01-25

申请号：US16789839

申请日：2020-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC: H01L49/02 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.

公开(公告)号：US11133374B2

公开(公告)日：2021-09-28

申请号：US16665894

申请日：2019-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Shuo Su ,  Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04

Abstract: A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.

公开(公告)号：US20210134940A1

公开(公告)日：2021-05-06

申请号：US16789839

申请日：2020-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC: H01L49/02 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.

公开(公告)号：US20210134875A1

公开(公告)日：2021-05-06

申请号：US16804208

申请日：2020-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiech-Fun Lu ,  Chun-Tsung Kuo

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.

公开(公告)号：US20210036043A1

公开(公告)日：2021-02-04

申请号：US17063801

申请日：2020-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Huang ,  Jiech-Fun Lu ,  Yu-Chun Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

公开(公告)号：US20200091223A1

公开(公告)日：2020-03-19

申请号：US16693627

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC: H01L27/146

Abstract: The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

公开(公告)号：US20200058746A1

公开(公告)日：2020-02-20

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/66 ,  H01L29/06

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US10461145B2

公开(公告)日：2019-10-29

申请号：US15880289

申请日：2018-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Shuo Su ,  Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04

Abstract: A method for fabricating a magnetic core includes depositing a magnetic layer on a dielectric layer, forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer, etching the magnetic layer through the patterned first photoresist layer, in which a first section of the magnetic layer exposed by the first photoresist layer remains on the dielectric layer after the magnetic layer is etched, removing the patterned first photoresist layer, forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer, etching the magnetic layer through the patterned second photoresist layer, and removing the second photoresist layer.

公开(公告)号：US20180269299A1

公开(公告)日：2018-09-20

申请号：US15463088

申请日：2017-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Wen Hsu ,  Hung-Ling Shih ,  Jiech-Fun Lu

IPC: H01L29/49 ,  H01L27/06 ,  H01L21/311 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.

公开(公告)号：US09893141B2

公开(公告)日：2018-02-13

申请号：US14632519

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Shuo Su ,  Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04

CPC classification number: H01L28/10 ,  H01F17/0033 ,  H01F41/046

Abstract: A magnetic core includes a center section having a substantially uniform thickness, and an edge section connected to and surrounding the center section. The edge section includes a bottom portion and a top portion disposed on the bottom portion, in which the bottom portion has a gradual side surface since the top portion has a steep side surface. The profile of the magnetic core can be more rectangular thereby providing better inductor performance.