公开(公告)号：US20210242153A1

公开(公告)日：2021-08-05

申请号：US17236360

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sin-Yao Huang ,  Jeng-Shyan Lin ,  Shih-Pei Chou ,  Tzu-Hsuan Hsu

IPC分类号： H01L23/00 ,  H01L27/146

摘要： Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

公开(公告)号：US20200091223A1

公开(公告)日：2020-03-19

申请号：US16693627

申请日：2019-11-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC分类号： H01L27/146

摘要： The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

公开(公告)号：US20200058746A1

公开(公告)日：2020-02-20

申请号：US16103101

申请日：2018-08-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/66 ,  H01L29/06

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US11264469B2

公开(公告)日：2022-03-01

申请号：US16861478

申请日：2020-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US10804315B2

公开(公告)日：2020-10-13

申请号：US16693627

申请日：2019-11-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC分类号： H01L27/146

摘要： The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

公开(公告)号：US10510799B2

公开(公告)日：2019-12-17

申请号：US16420576

申请日：2019-05-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC分类号： H01L27/146

摘要： The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.

公开(公告)号：US10395974B1

公开(公告)日：2019-08-27

申请号：US15962214

申请日：2018-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Pei Chou ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Yu-Hung Cheng ,  Yung-Lung Lin ,  Min-Ying Tsai

IPC分类号： H01L21/762 ,  H01L21/306

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.

公开(公告)号：US10312278B2

公开(公告)日：2019-06-04

申请号：US15644022

申请日：2017-07-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsun-Kai Tsao ,  Shih-Pei Chou ,  Jiech-Fun Lu

IPC分类号： H01L27/146

摘要： An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure includes a storage gate structure formed over the storage region, and the storage gate structure includes a top surface and sidewall surfaces. The FSI image sensor device structure includes a metal shield structure formed on the storage gate structure, and the top surface and the sidewall surfaces of the storage gate structure are covered by the metal shield structure.

公开(公告)号：US20180337211A1

公开(公告)日：2018-11-22

申请号：US15597452

申请日：2017-05-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC分类号： H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

摘要： In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.

公开(公告)号：US11776985B2

公开(公告)日：2023-10-03

申请号：US17313140

申请日：2021-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsun-Kai Tsao ,  Jiech-Fun Lu ,  Shih-Pei Chou ,  Wei Chuang Wu

IPC分类号： H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14623

摘要： A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.