公开(公告)号：US11264469B2

公开(公告)日：2022-03-01

申请号：US16861478

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20220102397A1

公开(公告)日：2022-03-31

申请号：US17036202

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L27/146

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

公开(公告)号：US20150001669A1

公开(公告)日：2015-01-01

申请号：US13930189

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.

Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离件位于半导体衬底中，并且包括底部和顶部。 底部具有衬里氧化物层，带负电的衬垫和第一氧化硅。 衬里氧化物层由半导体衬底外围封装，带负电的衬垫由衬里氧化物层周边封闭，第一氧化硅由带负电的衬垫周边封闭。 顶部邻接底部，并且具有由半导体衬底周围包围并接触的第二氧化硅。

公开(公告)号：US11955496B2

公开(公告)日：2024-04-09

申请号：US17036202

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

公开(公告)号：US20200058746A1

公开(公告)日：2020-02-20

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/66 ,  H01L29/06

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US09917003B2

公开(公告)日：2018-03-13

申请号：US13930189

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.

公开(公告)号：US09281331B2

公开(公告)日：2016-03-08

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L31/062 ,  H01L27/146 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。

公开(公告)号：US20150372034A1

公开(公告)日：2015-12-24

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/423 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。

公开(公告)号：US11063117B2

公开(公告)日：2021-07-13

申请号：US15492472

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Yong-En Syu ,  Kuo-Hwa Tzeng ,  Ke-Dian Wu ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ming-Che Yang ,  Wei-Kung Tsai

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.

公开(公告)号：US10658474B2

公开(公告)日：2020-05-19

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.