公开(公告)号：US11004959B2

公开(公告)日：2021-05-11

申请号：US16683512

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/033 ,  H01L21/8234

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.

公开(公告)号：US10930794B2

公开(公告)日：2021-02-23

申请号：US16358314

申请日：2019-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02

Abstract: A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.

公开(公告)号：US20210043626A1

公开(公告)日：2021-02-11

申请号：US17080387

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/32 ,  H01L21/3105

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US10680109B2

公开(公告)日：2020-06-09

申请号：US16141509

申请日：2018-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao Kuo ,  Jung-Hao Chang ,  Chao-Hsien Huang ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20200052132A1

公开(公告)日：2020-02-13

申请号：US16656367

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.

公开(公告)号：US10529833B2

公开(公告)日：2020-01-07

申请号：US15864525

申请日：2018-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Teng-Chun Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/161 ,  H01L27/088 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

公开(公告)号：US20190333821A1

公开(公告)日：2019-10-31

申请号：US16506808

申请日：2019-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

公开(公告)号：US10403545B2

公开(公告)日：2019-09-03

申请号：US15718740

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

公开(公告)号：US20190267375A1

公开(公告)日：2019-08-29

申请号：US16407751

申请日：2019-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/535 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308

Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

公开(公告)号：US20190097021A1

公开(公告)日：2019-03-28

申请号：US16201743

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench.