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    Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator
    15.
    发明授权
    Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator 有权

    公开(公告)号：US12164211B2

    公开(公告)日：2024-12-10

    申请号：US18128737

    申请日：2023-03-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Min-Hsiang Hsu

    IPC: G02F1/225 ,  G02F1/21

    Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.

    Two-dimensional grating coupler and methods of making same
    16.
    发明授权
    Two-dimensional grating coupler and methods of making same 有权

    公开(公告)号：US12085761B2

    公开(公告)日：2024-09-10

    申请号：US18201110

    申请日：2023-05-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Tsung Shih ,  Chewn-Pu Jou ,  Stefan Rusu ,  Felix Ying-Kit Tsui ,  Lan-Chou Cho

    IPC: G02B6/34 ,  G02B6/30

    CPC classification number: G02B6/34 ,  G02B6/305

    Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.

    APPARATUS, CIRCUITS AND METHODS FOR REDUCING MISMATCH IN AN ELECTRO-OPTIC MODULATOR
    17.
    发明公开
    APPARATUS, CIRCUITS AND METHODS FOR REDUCING MISMATCH IN AN ELECTRO-OPTIC MODULATOR 审中-公开

    公开(公告)号：US20230236468A1

    公开(公告)日：2023-07-27

    申请号：US18128737

    申请日：2023-03-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Min-Hsiang Hsu

    IPC: G02F1/225 ,  G02F1/21

    CPC classification number: G02F1/2255 ,  G02F1/212

    Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.

    Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator
    18.
    发明授权
    Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator 有权

    公开(公告)号：US11650476B2

    公开(公告)日：2023-05-16

    申请号：US17503095

    申请日：2021-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Min-Hsiang Hsu

    IPC: G02F1/225 ,  G02F1/21

    CPC classification number: G02F1/2255 ,  G02F1/212

    Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.

    All-digital phase locked loop using switched capacitor voltage doubler
    19.
    发明授权
    All-digital phase locked loop using switched capacitor voltage doubler 有权

    公开(公告)号：US11177810B2

    公开(公告)日：2021-11-16

    申请号：US17112450

    申请日：2020-12-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Feng Wei Kuo ,  Chewn-Pu Jou ,  Huan-Neng Chen ,  Lan-Chou Cho ,  Robert Bogdan Staszewski ,  Seyednaser Pourmousavian

    IPC: H03L7/06 ,  H03L1/00 ,  G04F10/00 ,  H03L7/099 ,  H03L7/093 ,  H03L7/08

    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

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