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    Cover ring and ground shield for physical vapor deposition chamber
    11.
    发明授权
    Cover ring and ground shield for physical vapor deposition chamber 有权

    公开(公告)号：US11569071B2

    公开(公告)日：2023-01-31

    申请号：US17214656

    申请日：2021-03-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tsung-Cheng Wu ,  Sheng-Ying Wu ,  Ming-Hsien Lin

    IPC: H01J37/32 ,  C23C14/35 ,  H01J37/34

    Abstract: A processing chamber includes a ground shield and a cover ring. The ground shield includes an annular body, and at least one guide pin extending from the annular body. The cover ring is positioned on the ground shield, and includes an annular body including at least one recess. At least a part of the at least one guide pin is receivable in the at least one recess, an inner cylindrical ring extends from the annular body, and an outer cylindrical ring extends from the annular body and is radially separated from the inner cylindrical ring by a horizontally extending portion of the annular body.

    Method for evaluating failure-in-time
    12.
    发明授权
    Method for evaluating failure-in-time 有权

    公开(公告)号：US11366951B2

    公开(公告)日：2022-06-21

    申请号：US17204275

    申请日：2021-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

    Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

    Enhancing Integrated Circuit Density with Active Atomic Reservoir
    14.
    发明申请
    Enhancing Integrated Circuit Density with Active Atomic Reservoir 审中-公开

    公开(公告)号：US20190287897A1

    公开(公告)日：2019-09-19

    申请号：US16429350

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ta-Pen Guo ,  Ming-Hsien Lin

    IPC: H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  H01L49/02 ,  H01L29/06 ,  H01L23/532

    Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

    Atomic Layer Deposition Based Process for Contact Barrier Layer
    15.
    发明申请
    Atomic Layer Deposition Based Process for Contact Barrier Layer 审中-公开

    公开(公告)号：US20190148153A1

    公开(公告)日：2019-05-16

    申请号：US16220247

    申请日：2018-12-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Yu-Lin Liu ,  Ming-Hsien Lin ,  Tzo-Hung Luo

    IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532

    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

    Threshold voltage tuning for fin-based integrated circuit device
    18.
    发明授权
    Threshold voltage tuning for fin-based integrated circuit device 有权

    公开(公告)号：US10790196B2

    公开(公告)日：2020-09-29

    申请号：US15808285

    申请日：2017-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L27/12

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

    Enhancing integrated circuit density with active atomic reservoir
    19.
    发明授权
    Enhancing integrated circuit density with active atomic reservoir 有权

    公开(公告)号：US10312189B2

    公开(公告)日：2019-06-04

    申请号：US15928909

    申请日：2018-03-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ta-Pen Guo ,  Ming-Hsien Lin

    IPC: H01L23/522 ,  H01L23/532 ,  H01L27/02 ,  H01L29/06 ,  H01L49/02 ,  H01L27/118

    Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.

    Semiconductor fabrication tool having gas manifold assembled by jig
    20.
    发明授权
    Semiconductor fabrication tool having gas manifold assembled by jig 有权

    公开(公告)号：US11587802B2

    公开(公告)日：2023-02-21

    申请号：US16749286

    申请日：2020-01-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ming-Che Chen ,  Wen-Tane Liao ,  Ming-Hsien Lin ,  Wei-Chen Liao ,  Hai-Lin Lee ,  Chun-Yu Chen

    IPC: H01L21/67

    Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

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